;=========================================
; NAME: 2440INIT.S
; DESC: C start up codes
; Configure memory, ISR ,stacks
; Initialize C-variables
;=========================================
; include ， Get
; *.h ， *.inc
GET option.inc ;
GET memcfg.inc ;
GET 2440addr.inc ;
;REFRESH [22]bit : 0- auto refresh; 1 - self refresh
BIT_SELFREFRESH EQU (1<<22) ; ，SDRAM
; : CPSR 5 M[4:0]
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f ;M[4:0]
NOINT EQU 0xc0
;
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ _STACK_BASEADDRESS option.inc
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
;arm 1.arm:32 arm 2.Thumb:16
; Thumb
; 16 32 16 32
;
;code16 16 thumb
;code32 32 arm
;
;Arm ARM ， ARM Thumb ， ARM ， init.s
; 。 ， THUMBCODE ， main
;
;
; （16 tasm.exe
;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE ; THUMBCODE EQU
[ {CONFIG} = 16 ; 16 （ thumb ）
THUMBCODE SETL {TRUE} ; THUMBCODE TURE
CODE32 ; ARM ，
| ;（| else） ARM
THUMBCODE SETL {FALSE} ; THUMBCODE FALSE
] ;
MACRO ; THUMBCODE PC LR
MOV_PC_LR ;
[ THUMBCODE ; THUMBCODE，
bx lr ; ARM BX THUMB , . bx PC 1 thumb
| ; ，
mov pc,lr ; ARM
]
MEND ;
MACRO ; ,
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr
|
moveq pc,lr
]
MEND
;=======================================================================================
; ,
; _ISR_STARTADDRESS=0x33FF_FF00 Handle*** .
; ENTRY ( ) b Handler*** .
; Handler*** HANDLER Handle*** .
; , ENTRY ROM(FLASH) ,
; , .
;========================================================================================
;; pc ， “ ”。
; （ ），34 ， 。
; ， Handle*** 。
; “ ” 。
;
; cpu 0x18 IRQ ， ;
; 0x18 ，
; ADC 0xC0, 0xC0
; ：ldr PC,=HandlerADC ADC
; HandlerADC
; ， ， interrupt
;pending 0x18
; interrupt pending
;
;
;H|------| H|------| H|------| H|------| H|------|
; |/ / / | |/ / / | |/ / / | |/ / / | |/ / / |
; |------|pc
; | | | | |--r0--|r0
; (0) (1) (2) (3) (4)
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel ;
sub sp,sp,#4 ;(1) sp( )
stmfd sp!,{r0} ;(2) (lr does not push because it return to original address)
ldr r0,=$HandleLabel; HandleXXX r0
ldr r0,[r0] ; HandleXXX ( ) r0
str r0,[sp,#4] ;(3) (ISR)
ldmfd sp!,{r0,pc} ;(4) r0 pc ( ISR )
MEND
;=========================================================================================
; IMPORT ( c extren ) |Image$$RO$$Base|,|Image$$RO$$Limit|...
; ADS RO Base RW Base ,
; .
; ,
;==========================================================================================
;Image$$RO$$Base 。RO, RW, ZI Flash ， RW，ZI Flash
; ， Flash RW，ZI RAM 。
; ， 。 main() ， b __Main, __Main
; Main ， RW，ZI 。 b Main， 。
; RO，RW，ZI ， RW，ZI Flash ，
; RW，ZI Flash RO 。 Image$$RO$$Base，Image$$RO$$Limit， Image$$RO$$Limit
; RW（ROM data） 。
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
; , main
;IMPORT MMU_SetAsyncBusMode
;IMPORT MMU_SetFastBusMode ;hzh
IMPORT Main
; !
AREA Init,CODE,READONLY ; Init
ENTRY ; ( )
EXPORT __ENTRY ; _ENTRY,
__ENTRY
ResetEntry
;1)The code, which converts to Big-endian, should be in little endian code.
;2)The following little endian code will be compiled in Big-Endian mode.
; The code byte order should be changed as the memory bus width.
;3)The pseudo instruction,DCD can not be used here because the linker generates error.
; ，
ASSERT :DEF:ENDIAN_CHANGE ; ENDIAN_CHANGE
[ ENDIAN_CHANGE ; ENDIAN_CHANGE， （ Option.inc FALSE ）
ASSERT :DEF:ENTRY_BUS_WIDTH ; ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32 ; ENTRY_BUS_WIDTH， 32
b ChangeBigEndian ;DCD 0xea000007
]
; bigendian ， A A，A+1，A+2，A+3， A，A+1，A+2，A+3
; A A，A+2， A，A+2
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00 b ChangeBigEndian ，
] ; ->
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea b ChangeBigEndian ，
]
|
b ResetHandler ; ENDIAN_CHANGE FALSE ,
]
b HandlerUndef ;handler for Undefined mode ;0x04
b HandlerSWI ;handler for SWI interrupt ;0x08
b HandlerPabort ;handler for PAbort ;0x0c
b HandlerDabort ;handler for DAbort ;0x10
b . ;reserved ;0x14
b HandlerIRQ ;handler for IRQ interrupt ;0x18
b HandlerFIQ ;handler for FIQ interrupt ;0x1c
;@0x20
b EnterPWDN ; Must be @0x20.
;==================================================================================
; , ,
; ,
;==================================================================================
; CP15 C1 7， Bigendian，
ChangeBigEndian ;//here ENTRY_BUS_WIDTH=16
;@0x24
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0
; ， Big-endian
; CPU 32 ， ，CPU ，
; ， CPU
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
; Big-endian ， 16 ，
;
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
;=========================================================================================
; Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON 0x4c00000c
tst r0,#0x8 ; bit[3] SLEEP mode? 1=>sleep
bne ENTER_SLEEP ;C=0, TST 0，bit[3]=1
;// PWDN sleep stop
;// Stop mode
ENTER_STOP
ldr r0,=REFRESH ;0x48000024 DRAM/SDRAM refresh config
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH ;Enable SDRAM self-refresh
str r1, [r0] ;Enable SDRAM self-refresh
mov r1,#16 ;wait until self-refresh is issued. may not be needed.
0
subs r1,r1,#1
bne %B0
;//wait 16 fclks for self-refresh
ldr r0,=CLKCON ;enter STOP mode.
str r2,[r0]
mov r1,#32
0
subs r1,r1,#1 ;1) wait until the STOP mode is in effect.
bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off
;Entering SLEEP mode, only the reset by wake-up is available.
ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
str r3,[r0]
MOV_PC_LR ;back to main process
ENTER_SLEEP
;NOTE.
;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.
ldr r0,=REFRESH
ldr r1,[r0] ;r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh
;//Enable SDRAM self-refresh
mov r1,#16 ;Wait until self-refresh is issued,which may not be needed.
0
subs r1,r1,#1
bne %B0
;//Wait until self-refresh is issued,which may not be needed
ldr r1,=MISCCR ;IO register
ldr r0,[r1]
orr r0,r0,#(7<<17) ;Set SCLK0=1, SCLK1=1, SCKE=1.
str r0,[r1]
ldr r0,=CLKCON ; Enter sleep mode
str r2,[r0]
b . ;CPU will die here.
;// Sleep Mode，1） SDRAM self-refresh
;// 2） MISCCR bit[17] 1:sclk0=sclk 0:sclk0=0
;// bit[18] 1:sclk1=sclk 0:sclk1=0
;// bit[19] 1:Self refresh retain enable
;// 0:Self refresh retain disable
;// When 1, After wake-up from sleep, The self-refresh will be retained.
WAKEUP_SLEEP
;Release SCLKn after wake-up from the SLEEP mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
str r0,[r1]
;// MISCCR
;Set memory control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA
ldr r1,=BWSCON ;BWSCON Address ;//
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4 ; R0 4，[R0]->R3，R0+4->R0
str r3, [r1], #4
cmp r2, r0
bne %B0
;// memory control register， BWSCON，
;// SMRDATA
mov r1,#256
0
subs r1,r1,#1 ;1) wait until the SelfRefresh is released.
bne %B0
;//1) wait until the SelfRefresh is released.
ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up
ldr r0,[r1]
mov pc,r0
;// Sleep Mode， Sleep PC
;============================================================================================
; , HANDLER Hander*** Handle***
LTORG ; , ldr
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
;===================================================================================
; , . , .
; , .
; ??
; ,ARM IRQ FIRQ
; , !
; , !
;===================================================================================
;// ，
;//PC=[HandleEINT0+[INTOFFSET]]
;H|------|
; |/ / / |
; |--isr-| ====>pc
;L|--r8--|
; |--r9--|1 ; Fclk:Hclk 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
; == 243 ==
; If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous
; bus mode using following instructions
;MMU_SetAsyncBusMode
;mrc p15,0,r0,c1,c0,0
;orr r0,r0,#R1_nF:OR:R1_iA
;mcr p15,0,r0,c1,c0,0
[ CLKDIV_VAL>1 ; Fclk:Hclk 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
; UPLL
;//Configure UPLL Fin=12.0MHz UFout=48MHz
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;//USB PLL CONFIG 56,2,2===>48MHz
str r1,[r0]
;7 nop ！！
nop ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
; MPLL
;//Configure MPLL Fin=12.0MHz MFout=304.8MHz
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;68,1,1 ==>304MHz
str r1,[r0]
]
; SLEEP
;//Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2 ;test if bit[1] is 1 or 0 0->C=1
; 1->C=0
;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP ;C=0,jump
EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
;===============================================================================
; , ,
; . SMRDATA ,
;===============================================================================
; SDRAM,flash ROM ,
;SMRDATA map
;SMRDATA memcfg.inc
;Set memory control registers
;ldr r0,=SMRDATA ;dangerous!!!
adrl r0, SMRDATA ;be careful!, tinko
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA ;SMRDATA , 52
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0 ;% ，B -back(F -forward)，0 (0~99)
;================================================================================
; EINT0 ( ), SDRAM ,
;================================================================================
; check if EIN0 button is pressed
ldr r0,=GPFCON
ldr r1,=0x0 ;00 = Input
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff ;1- The pull up function is disabled.
str r1,[r0]
ldr r1,=GPFDAT
ldr r0,[r1]
bic r0,r0,#(0x1e<<1) ; bit clear
tst r0,#0x1
bne %F1 ; , 1 => Initialize stacks
;
ldr r0,=GPFCON
ldr r1,=0x55aa
str r1,[r0]
; ldr r0,=GPFUP
; ldr r1,=0xff
; str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;LED=****
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
ldr r9,=0x4000000 ;64MB
ldr r0,=0x30000000
0
stmia r0!,{r1-r8}
subs r9,r9,#32
bne %B0
; .
;//4.
;Initialize stacks
1
bl InitStacks
;=======================================================================
; , , hzh
; NOR NAND , , .
; NOR NAND .
; , |Image$$RO$$Base|,|Image$$RO$$Limit|... ?
; !!!
;=========================================================================
;BWSCON [2:1] OM[1:0]: OM[1:0] != 00, NOR FLash ； OM[1:0]==00， Nand Flash Mode
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ; #6 == 0110 --> BWSCON[2:1]
bne copy_proc_beg ;OM[1:0] != 00，NOR FLash boot， NAND FLASH
adr r0, ResetEntry ; ,OM[1:0] == 0, NAND FLash
cmp r0, #0 ; 0
; 0 NAND ， 4k 0 stepingstone sram
; adr ， == if use Multi-ice,
bne copy_proc_beg ; !=0, using ice, NAND FLASH. don't read nand flash for boot
;nop
;============== NAND Flash RAM=====================
nand_boot_beg ;
mov r5, #NFCONF ; NAND
;set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID ; NAND ID , r5
mov r6, #0 ;r6 0.
ldr r0, =0xec73 ; NAND ID
cmp r5, r0 ;
beq %F1 ; 1
ldr r0, =0xec75 ;
cmp r5, r0
beq %F1 ; 1
mov r6, #1 ; , r6=1.
1
bl ReadNandStatus ; NAND , r1
mov r8, #0 ; r8 0,
ldr r9, =ResetEntry ; r9
; , ldr , adr , ResetEntry
; , RAM , , |Image$$RO$$Base|
; , RO base RAM ,
; NAND , ldr r9 . ???
2
ands r0, r8, #0x1f ; r8 0x1f(32) -1,eq ,ne
bne %F3 ; (32 ) --
mov r0, r8 ;r8->r0
bl CheckBadBlk ; NAND
cmp r0, #0 ; r0 0
addne r8, r8, #32 ; : + 32 . : r8 = blockpage addr， ( 512Byte)
bne %F4 ; 4 。 3 copy
3
mov r0, r8 ; ->r0
mov r1, r9 ; ->r1
bl ReadNandPage ; NAND RAM
add r9, r9, #512 ; 512Bytes
add r8, r8, #1 ;r8
4
cmp r8, #256 ; 256 128KBytes
; ： 128KByte (by Tinko)
bcc %B2 ; r8 256( ), 2
; now copy completed
mov r5, #NFCONF ;Disable NandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]
ldr pc, =copy_proc_beg ; copy_proc_beg
; InitRam ?????????????????????????????
;===========================================================
copy_proc_beg
adrl r0, ResetEntry ;ResetEntry ->r0
; ， adr， ldr。 ldr ResetEntry ，
; 。 adr ResetEntry ， 。
; stepingstone ， ResetEntry 。 RAM ， ResetEntry ＲＡＭ
; ， RO base。
ldr r2, BaseOfROM ;BaseOfROM ( )->r2
cmp r0, r2 ; ResetEntry BaseOfROM
ldreq r0, TopOfROM ; ( --- ice -- code ro ， code rw ),TopOfROM->r0
beq InitRam ; InitRam
; ， code RO
;=========================================================
; NOR FLASH
; ResetEntry ,TopOfROM-BaseOfROM BaseOfROM
;TopOfROM BaseOfROM |Image$$RO$$Limit| |Image$$RO$$Base|
;|Image$$RO$$Limit| |Image$$RO$$Base|
;
;BaseOfBSS BaseOfZero |Image$$RW$$Base| |Image$$ZI$$Base|
;|Image$$RW$$Base| |Image$$ZI$$Base|
;
; -- ， ZI --
;=======================================================
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7} ; ，r0 = ResetEntry --- source
stmia r2!, {r4-r7} ; ，r2 = BaseOfROM --- destination
cmp r2, r3 ; ： TopOfROM-BaseOfROM
bcc %B0
;---------------------------------------------------------------
; 2 ， ， tinko
; " ! "， 。
;---------------------------------------------------------------
adrl r0, ResetEntry ;don't use adr, 'cause out of range error occures
ldr r2, BaseOfROM
; RW
; 2 r0（ code rw ）
sub r2, r2, r3 ;r2=BaseOfROM-TopOfROM=(-)
sub r0, r0, r2 ;r0=ResetEntry-(-) =ResetEntry+
InitRam
; RM |Image$$RW$$Base|
ldr r2, BaseOfBSS ;BaseOfBSS->r2 , BaseOfBSS = |Image$$RW$$Base|
ldr r3, BaseOfZero ;BaseOfZero->r3 , BaseOfZero = |Image$$ZI$$Base|
0
cmp r2, r3 ; BaseOfBSS BaseOfZero
ldrcc r1, [r0], #4 ; ，r0( ) = TopOfROM. BaseOfZero-BaseOfBSS code， BaseOfBSS
strcc r1, [r2], #4
bcc %B0
; 0 ZI
mov r0, #0
ldr r3, EndOfBSS ;EndOfBSS = |Image$$ZI$$Limit|
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
; r21 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
;bl Led_Test
;===========================================================
; C ,
; ( ) .
;//5.
; Setup IRQ handler
ldr r0,=HandleIRQ ;This routine is needed
ldr r1,=IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
;//initialize the IRQ HandleIRQ
;//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
; ， !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;//6. ram C main bootloader
;If main() is used, the variable initialization will be done in __main().
[ {FALSE} ;by tinko -- tinko ，
[ :LNOT:USE_MAIN ;initialized {FALSE}
;Copy and paste RW data/zero initialized data
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different just for debug??????????????????????????
BEQ %F2
1
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
BCC %B1
2
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
3
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %B3
]
]
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;***************************************
;by tinko
[ {TRUE} ; , LED
;rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
; Led_Display
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0xe0
str r1,[r0]
ldr r2, =0xffffffff;
1
sub r2,r2,#1
bne %b1
ldr r0,=GPFDAT
ldr r1,=0xe0
;b . ;die here
]
;*****************************************
;*****************************************************************************
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
; , !!!!!!!!!!
; C main .
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;*****************************************************************************
[ :LNOT:THUMBCODE ;if thumbcode={false} bl main L logic
bl Main ;Don't use main() because ......
b . ;
]
;//if thumbcod={ture}
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Don't use main() because ......
b . ;
CODE32
]
;function initializing stacks
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;// user stacks， ？
mov pc,lr
;The LR register won't be valid if the current mode is not SVC mode.？
;// SVCmode？
;===========================================================
ReadNandID
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x90 ;WrNFCmd(RdIDCMD);
strb r0,[r7,#8]
mov r4,#0 ;WrNFAddr(0);
strb r4,[r7,#0xc]
1 ;while(NFIsBusy());
ldr r0,[r7,#0x20]
tst r0,#1
beq %B1
ldrb r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0x10] ;id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
ReadNandStatus
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
strb r0,[r7,#8]
ldrb r1,[r7,#0x10] ;r1 = RdNFDat();
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
WaitNandBusy
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
mov r1,#NFCONF
strb r0,[r1,#8]
1 ;while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0x10]
tst r0,#0x40
beq %B1
mov r0,#0 ;WrNFCmd(READCMD0);
strb r0,[r1,#8]
mov pc,lr
CheckBadBlk
mov r7, lr
mov r5, #NFCONF
bic r0,r0,#0x1f ;addr &= ~0x1f;
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0x50 ;WrNFCmd(READCMD2)
strb r1,[r5,#8]
mov r1, #5;6 ;6->5
strb r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne %B1
2
ldr r0, [r5, #0x20]
tst r0, #1
beq %B2
ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
ldr r1,[r5,#4] ;NFChipDs()
orr r1,r1,#2
str r1,[r5,#4]
mov pc, r7
ReadNandPage
mov r7,lr
mov r4,r1
mov r5,#NFCONF
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
strb r1,[r5,#0xc] ;WrNFAddr(0)
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
ldr r0,[r5,#4] ;InitEcc()
orr r0,r0,#0x10
str r0,[r5,#4]
bl WaitNandBusy ;WaitNFBusy()
mov r0,#0 ;for(i=0; i<512; i++)
1
ldrb r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
bic r0,r0,#0x10000
cmp r0,#0x200
bcc %B1
ldr r0,[r5,#4] ;NFChipDs()
orr r0,r0,#2
str r0,[r5,#4]
mov pc,r7
;--------------------LED test
EXPORT Led_Test
Led_Test
mov r0, #0x56000000
mov r1, #0x5500
str r1, [r0, #0x50]
0
mov r1, #0x50
str r1, [r0, #0x54]
mov r2, #0x100000
1
subs r2, r2, #1
bne %B1
mov r1, #0xa0
str r1, [r0, #0x54]
mov r2, #0x100000
2
subs r2, r2, #1
bne %B2
b %B0
mov pc, lr
;===========================================================
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144
CLKDIV124
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKDIV144
ldr r0, = CLKDIVN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
;
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+ (B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+ (B6_BWSCON<<24)+(B7_BWSCON<<28)) ; bank bus width; B0， OM[1:0]pins
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6 B6_MT memcfg.inc ，11-->SDRAM ; B6_SCAN - reset
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;Tchr- not used
;DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x31 ;SCLK power saving mode, BANKSIZE 64M/64M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode
; 2003.03.14:DonGo: Modified for 2440.
; 2009 06.24:Tinko Modified
;=========================================
; include ， Get
; *.h ， *.inc
GET option.inc ;
GET memcfg.inc ;
GET 2440addr.inc ;
;REFRESH [22]bit : 0- auto refresh; 1 - self refresh
BIT_SELFREFRESH EQU (1<<22) ; ，SDRAM
; : CPSR 5 M[4:0]
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f ;M[4:0]
NOINT EQU 0xc0
;
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ _STACK_BASEADDRESS option.inc
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
;arm 1.arm:32 arm 2.Thumb:16
; Thumb
; 16 32 16 32
;
;code16 16 thumb
;code32 32 arm
;
;Arm ARM ， ARM Thumb ， ARM ， init.s
; 。 ， THUMBCODE ， main
;
;
; （16 tasm.exe
;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE ; THUMBCODE EQU
[ {CONFIG} = 16 ; 16 （ thumb ）
THUMBCODE SETL {TRUE} ; THUMBCODE TURE
CODE32 ; ARM ，
| ;（| else） ARM
THUMBCODE SETL {FALSE} ; THUMBCODE FALSE
] ;
MACRO ; THUMBCODE PC LR
MOV_PC_LR ;
[ THUMBCODE ; THUMBCODE，
bx lr ; ARM BX THUMB , . bx PC 1 thumb
| ; ，
mov pc,lr ; ARM
]
MEND ;
MACRO ; ,
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr
|
moveq pc,lr
]
MEND
;=======================================================================================
; ,
; _ISR_STARTADDRESS=0x33FF_FF00 Handle*** .
; ENTRY ( ) b Handler*** .
; Handler*** HANDLER Handle*** .
; , ENTRY ROM(FLASH) ,
; , .
;========================================================================================
;; pc ， “ ”。
; （ ），34 ， 。
; ， Handle*** 。
; “ ” 。
;
; cpu 0x18 IRQ ， ;
; 0x18 ，
; ADC 0xC0, 0xC0
; ：ldr PC,=HandlerADC ADC
; HandlerADC
; ， ， interrupt
;pending 0x18
; interrupt pending
;
;
;H|------| H|------| H|------| H|------| H|------|
; |/ / / | |/ / / | |/ / / | |/ / / | |/ / / |
; |------|pc
; | | | | |--r0--|r0
; (0) (1) (2) (3) (4)
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel ;
sub sp,sp,#4 ;(1) sp( )
stmfd sp!,{r0} ;(2) (lr does not push because it return to original address)
ldr r0,=$HandleLabel; HandleXXX r0
ldr r0,[r0] ; HandleXXX ( ) r0
str r0,[sp,#4] ;(3) (ISR)
ldmfd sp!,{r0,pc} ;(4) r0 pc ( ISR )
MEND
;=========================================================================================
; IMPORT ( c extren ) |Image$$RO$$Base|,|Image$$RO$$Limit|...
; ADS RO Base RW Base ,
; .
; ,
;==========================================================================================
;Image$$RO$$Base 。RO, RW, ZI Flash ， RW，ZI Flash
; ， Flash RW，ZI RAM 。
; ， 。 main() ， b __Main, __Main
; Main ， RW，ZI 。 b Main， 。
; RO，RW，ZI ， RW，ZI Flash ，
; RW，ZI Flash RO 。 Image$$RO$$Base，Image$$RO$$Limit， Image$$RO$$Limit
; RW（ROM data） 。
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
; , main
;IMPORT MMU_SetAsyncBusMode
;IMPORT MMU_SetFastBusMode ;hzh
IMPORT Main
; !
AREA Init,CODE,READONLY ; Init
ENTRY ; ( )
EXPORT __ENTRY ; _ENTRY,
__ENTRY
ResetEntry
;1)The code, which converts to Big-endian, should be in little endian code.
;2)The following little endian code will be compiled in Big-Endian mode.
; The code byte order should be changed as the memory bus width.
;3)The pseudo instruction,DCD can not be used here because the linker generates error.
; ，
ASSERT :DEF:ENDIAN_CHANGE ; ENDIAN_CHANGE
[ ENDIAN_CHANGE ; ENDIAN_CHANGE， （ Option.inc FALSE ）
ASSERT :DEF:ENTRY_BUS_WIDTH ; ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32 ; ENTRY_BUS_WIDTH， 32
b ChangeBigEndian ;DCD 0xea000007
]
; bigendian ， A A，A+1，A+2，A+3， A，A+1，A+2，A+3
; A A，A+2， A，A+2
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00 b ChangeBigEndian ，
] ; ->
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea b ChangeBigEndian ，
]
|
b ResetHandler ; ENDIAN_CHANGE FALSE ,
]
b HandlerUndef ;handler for Undefined mode ;0x04
b HandlerSWI ;handler for SWI interrupt ;0x08
b HandlerPabort ;handler for PAbort ;0x0c
b HandlerDabort ;handler for DAbort ;0x10
b . ;reserved ;0x14
b HandlerIRQ ;handler for IRQ interrupt ;0x18
b HandlerFIQ ;handler for FIQ interrupt ;0x1c
;@0x20
b EnterPWDN ; Must be @0x20.
;==================================================================================
; , ,
; ,
;==================================================================================
; CP15 C1 7， Bigendian，
ChangeBigEndian ;//here ENTRY_BUS_WIDTH=16
;@0x24
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0
; ， Big-endian
; CPU 32 ， ，CPU ，
; ， CPU
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
; Big-endian ， 16 ，
;
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
;=========================================================================================
; Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON 0x4c00000c
tst r0,#0x8 ; bit[3] SLEEP mode? 1=>sleep
bne ENTER_SLEEP ;C=0, TST 0，bit[3]=1
;// PWDN sleep stop
;// Stop mode
ENTER_STOP
ldr r0,=REFRESH ;0x48000024 DRAM/SDRAM refresh config
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH ;Enable SDRAM self-refresh
str r1, [r0] ;Enable SDRAM self-refresh
mov r1,#16 ;wait until self-refresh is issued. may not be needed.
0
subs r1,r1,#1
bne %B0
;//wait 16 fclks for self-refresh
ldr r0,=CLKCON ;enter STOP mode.
str r2,[r0]
mov r1,#32
0
subs r1,r1,#1 ;1) wait until the STOP mode is in effect.
bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off
;Entering SLEEP mode, only the reset by wake-up is available.
ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
str r3,[r0]
MOV_PC_LR ;back to main process
ENTER_SLEEP
;NOTE.
;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.
ldr r0,=REFRESH
ldr r1,[r0] ;r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh
;//Enable SDRAM self-refresh
mov r1,#16 ;Wait until self-refresh is issued,which may not be needed.
0
subs r1,r1,#1
bne %B0
;//Wait until self-refresh is issued,which may not be needed
ldr r1,=MISCCR ;IO register
ldr r0,[r1]
orr r0,r0,#(7<<17) ;Set SCLK0=1, SCLK1=1, SCKE=1.
str r0,[r1]
ldr r0,=CLKCON ; Enter sleep mode
str r2,[r0]
b . ;CPU will die here.
;// Sleep Mode，1） SDRAM self-refresh
;// 2） MISCCR bit[17] 1:sclk0=sclk 0:sclk0=0
;// bit[18] 1:sclk1=sclk 0:sclk1=0
;// bit[19] 1:Self refresh retain enable
;// 0:Self refresh retain disable
;// When 1, After wake-up from sleep, The self-refresh will be retained.
WAKEUP_SLEEP
;Release SCLKn after wake-up from the SLEEP mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
str r0,[r1]
;// MISCCR
;Set memory control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA
ldr r1,=BWSCON ;BWSCON Address ;//
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4 ; R0 4，[R0]->R3，R0+4->R0
str r3, [r1], #4
cmp r2, r0
bne %B0
;// memory control register， BWSCON，
;// SMRDATA
mov r1,#256
0
subs r1,r1,#1 ;1) wait until the SelfRefresh is released.
bne %B0
;//1) wait until the SelfRefresh is released.
ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up
ldr r0,[r1]
mov pc,r0
;// Sleep Mode， Sleep PC
;============================================================================================
; , HANDLER Hander*** Handle***
LTORG ; , ldr
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
;===================================================================================
; , . , .
; , .
; ??
; ,ARM IRQ FIRQ
; , !
; , !
;===================================================================================
;// ，
;//PC=[HandleEINT0+[INTOFFSET]]
;H|------|
; |/ / / |
; |--isr-| ====>pc
;L|--r8--|
; |--r9--|1 ; Fclk:Hclk 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
; == 243 ==
; If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous
; bus mode using following instructions
;MMU_SetAsyncBusMode
;mrc p15,0,r0,c1,c0,0
;orr r0,r0,#R1_nF:OR:R1_iA
;mcr p15,0,r0,c1,c0,0
[ CLKDIV_VAL>1 ; Fclk:Hclk 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
; UPLL
;//Configure UPLL Fin=12.0MHz UFout=48MHz
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;//USB PLL CONFIG 56,2,2===>48MHz
str r1,[r0]
;7 nop ！！
nop ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
; MPLL
;//Configure MPLL Fin=12.0MHz MFout=304.8MHz
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;68,1,1 ==>304MHz
str r1,[r0]
]
; SLEEP
;//Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2 ;test if bit[1] is 1 or 0 0->C=1
; 1->C=0
;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP ;C=0,jump
EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
;===============================================================================
; , ,
; . SMRDATA ,
;===============================================================================
; SDRAM,flash ROM ,
;SMRDATA map
;SMRDATA memcfg.inc
;Set memory control registers
;ldr r0,=SMRDATA ;dangerous!!!
adrl r0, SMRDATA ;be careful!, tinko
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA ;SMRDATA , 52
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0 ;% ，B -back(F -forward)，0 (0~99)
;================================================================================
; EINT0 ( ), SDRAM ,
;================================================================================
; check if EIN0 button is pressed
ldr r0,=GPFCON
ldr r1,=0x0 ;00 = Input
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff ;1- The pull up function is disabled.
str r1,[r0]
ldr r1,=GPFDAT
ldr r0,[r1]
bic r0,r0,#(0x1e<<1) ; bit clear
tst r0,#0x1
bne %F1 ; , 1 => Initialize stacks
;
ldr r0,=GPFCON
ldr r1,=0x55aa
str r1,[r0]
; ldr r0,=GPFUP
; ldr r1,=0xff
; str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;LED=****
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
ldr r9,=0x4000000 ;64MB
ldr r0,=0x30000000
0
stmia r0!,{r1-r8}
subs r9,r9,#32
bne %B0
; .
;//4.
;Initialize stacks
1
bl InitStacks
;=======================================================================
; , , hzh
; NOR NAND , , .
; NOR NAND .
; , |Image$$RO$$Base|,|Image$$RO$$Limit|... ?
; !!!
;=========================================================================
;BWSCON [2:1] OM[1:0]: OM[1:0] != 00, NOR FLash ； OM[1:0]==00， Nand Flash Mode
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ; #6 == 0110 --> BWSCON[2:1]
bne copy_proc_beg ;OM[1:0] != 00，NOR FLash boot， NAND FLASH
adr r0, ResetEntry ; ,OM[1:0] == 0, NAND FLash
cmp r0, #0 ; 0
; 0 NAND ， 4k 0 stepingstone sram
; adr ， == if use Multi-ice,
bne copy_proc_beg ; !=0, using ice, NAND FLASH. don't read nand flash for boot
;nop
;============== NAND Flash RAM=====================
nand_boot_beg ;
mov r5, #NFCONF ; NAND
;set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID ; NAND ID , r5
mov r6, #0 ;r6 0.
ldr r0, =0xec73 ; NAND ID
cmp r5, r0 ;
beq %F1 ; 1
ldr r0, =0xec75 ;
cmp r5, r0
beq %F1 ; 1
mov r6, #1 ; , r6=1.
1
bl ReadNandStatus ; NAND , r1
mov r8, #0 ; r8 0,
ldr r9, =ResetEntry ; r9
; , ldr , adr , ResetEntry
; , RAM , , |Image$$RO$$Base|
; , RO base RAM ,
; NAND , ldr r9 . ???
2
ands r0, r8, #0x1f ; r8 0x1f(32) -1,eq ,ne
bne %F3 ; (32 ) --
mov r0, r8 ;r8->r0
bl CheckBadBlk ; NAND
cmp r0, #0 ; r0 0
addne r8, r8, #32 ; : + 32 . : r8 = blockpage addr， ( 512Byte)
bne %F4 ; 4 。 3 copy
3
mov r0, r8 ; ->r0
mov r1, r9 ; ->r1
bl ReadNandPage ; NAND RAM
add r9, r9, #512 ; 512Bytes
add r8, r8, #1 ;r8
4
cmp r8, #256 ; 256 128KBytes
; ： 128KByte (by Tinko)
bcc %B2 ; r8 256( ), 2
; now copy completed
mov r5, #NFCONF ;Disable NandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]
ldr pc, =copy_proc_beg ; copy_proc_beg
; InitRam ?????????????????????????????
;===========================================================
copy_proc_beg
adrl r0, ResetEntry ;ResetEntry ->r0
; ， adr， ldr。 ldr ResetEntry ，
; 。 adr ResetEntry ， 。
; stepingstone ， ResetEntry 。 RAM ， ResetEntry ＲＡＭ
; ， RO base。
ldr r2, BaseOfROM ;BaseOfROM ( )->r2
cmp r0, r2 ; ResetEntry BaseOfROM
ldreq r0, TopOfROM ; ( --- ice -- code ro ， code rw ),TopOfROM->r0
beq InitRam ; InitRam
; ， code RO
;=========================================================
; NOR FLASH
; ResetEntry ,TopOfROM-BaseOfROM BaseOfROM
;TopOfROM BaseOfROM |Image$$RO$$Limit| |Image$$RO$$Base|
;|Image$$RO$$Limit| |Image$$RO$$Base|
;
;BaseOfBSS BaseOfZero |Image$$RW$$Base| |Image$$ZI$$Base|
;|Image$$RW$$Base| |Image$$ZI$$Base|
;
; -- ， ZI --
;=======================================================
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7} ; ，r0 = ResetEntry --- source
stmia r2!, {r4-r7} ; ，r2 = BaseOfROM --- destination
cmp r2, r3 ; ： TopOfROM-BaseOfROM
bcc %B0
;---------------------------------------------------------------
; 2 ， ， tinko
; " ! "， 。
;---------------------------------------------------------------
adrl r0, ResetEntry ;don't use adr, 'cause out of range error occures
ldr r2, BaseOfROM
; RW
; 2 r0（ code rw ）
sub r2, r2, r3 ;r2=BaseOfROM-TopOfROM=(-)
sub r0, r0, r2 ;r0=ResetEntry-(-) =ResetEntry+
InitRam
; RM |Image$$RW$$Base|
ldr r2, BaseOfBSS ;BaseOfBSS->r2 , BaseOfBSS = |Image$$RW$$Base|
ldr r3, BaseOfZero ;BaseOfZero->r3 , BaseOfZero = |Image$$ZI$$Base|
0
cmp r2, r3 ; BaseOfBSS BaseOfZero
ldrcc r1, [r0], #4 ; ，r0( ) = TopOfROM. BaseOfZero-BaseOfBSS code， BaseOfBSS
strcc r1, [r2], #4
bcc %B0
; 0 ZI
mov r0, #0
ldr r3, EndOfBSS ;EndOfBSS = |Image$$ZI$$Limit|
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
; r21 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
;bl Led_Test
;=========;=========================================
; NAME: 2440INIT.S
; DESC: C start up codes
; Configure memory, ISR ,stacks
; Initialize C-variables
;
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode
; 2003.03.14:DonGo: Modified for 2440.
; 2009 06.24:Tinko Modified
;=========================================
; include ， Get
; *.h ， *.inc
GET option.inc ;
GET memcfg.inc ;
GET 2440addr.inc ;
;REFRESH [22]bit : 0- auto refresh; 1 - self refresh
BIT_SELFREFRESH EQU (1<<22) ; ，SDRAM
; : CPSR 5 M[4:0]
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f ;M[4:0]
NOINT EQU 0xc0
;
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ _STACK_BASEADDRESS option.inc
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
;arm 1.arm:32 arm 2.Thumb:16
; Thumb
; 16 32 16 32
;
;code16 16 thumb
;code32 32 arm
;
;Arm ARM ， ARM Thumb ， ARM ， init.s
; 。 ， THUMBCODE ， main
;
;
; （16 tasm.exe
;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE ; THUMBCODE EQU
[ {CONFIG} = 16 ; 16 （ thumb ）
THUMBCODE SETL {TRUE} ; THUMBCODE TURE
CODE32 ; ARM ，
| ;（| else） ARM
THUMBCODE SETL {FALSE} ; THUMBCODE FALSE
] ;
MACRO ; THUMBCODE PC LR
MOV_PC_LR ;
[ THUMBCODE ; THUMBCODE，
bx lr ; ARM BX THUMB , . bx PC 1 thumb
| ; ，
mov pc,lr ; ARM
]
MEND ;
MACRO ; ,
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr
|
moveq pc,lr
]
MEND
;=======================================================================================
; ,
; _ISR_STARTADDRESS=0x33FF_FF00 Handle*** .
; ENTRY ( ) b Handler*** .
; Handler*** HANDLER Handle*** .
; , ENTRY ROM(FLASH) ,
; , .
;========================================================================================
;; pc ， “ ”。
; （ ），34 ， 。
; ， Handle*** 。
; “ ” 。
;
; cpu 0x18 IRQ ， ;
; 0x18 ，
; ADC 0xC0, 0xC0
; ：ldr PC,=HandlerADC ADC
; HandlerADC
; ， ， interrupt
;pending 0x18
; interrupt pending
;
;
;H|------| H|------| H|------| H|------| H|------|
; |/ / / | |/ / / | |/ / / | |/ / / | |/ / / |
; |------|pc
; | | | | |--r0--|r0
; (0) (1) (2) (3) (4)
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel ;
sub sp,sp,#4 ;(1) sp( )
stmfd sp!,{r0} ;(2) (lr does not push because it return to original address)
ldr r0,=$HandleLabel; HandleXXX r0
ldr r0,[r0] ; HandleXXX ( ) r0
str r0,[sp,#4] ;(3) (ISR)
ldmfd sp!,{r0,pc} ;(4) r0 pc ( ISR )
MEND
;=========================================================================================
; IMPORT ( c extren ) |Image$$RO$$Base|,|Image$$RO$$Limit|...
; ADS RO Base RW Base ,
; .
; ,
;==========================================================================================
;Image$$RO$$Base 。RO, RW, ZI Flash ， RW，ZI Flash
; ， Flash RW，ZI RAM 。
; ， 。 main() ， b __Main, __Main
; Main ， RW，ZI 。 b Main， 。
; RO，RW，ZI ， RW，ZI Flash ，
; RW，ZI Flash RO 。 Image$$RO$$Base，Image$$RO$$Limit， Image$$RO$$Limit
; RW（ROM data） 。
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
; , main
;IMPORT MMU_SetAsyncBusMode
;IMPORT MMU_SetFastBusMode ;hzh
IMPORT Main
; !
AREA Init,CODE,READONLY ; Init
ENTRY ; ( )
EXPORT __ENTRY ; _ENTRY,
__ENTRY
ResetEntry
;1)The code, which converts to Big-endian, should be in little endian code.
;2)The following little endian code will be compiled in Big-Endian mode.
; The code byte order should be changed as the memory bus width.
;3)The pseudo instruction,DCD can not be used here because the linker generates error.
; ，
ASSERT :DEF:ENDIAN_CHANGE ; ENDIAN_CHANGE
[ ENDIAN_CHANGE ; ENDIAN_CHANGE， （ Option.inc FALSE ）
ASSERT :DEF:ENTRY_BUS_WIDTH ; ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32 ; ENTRY_BUS_WIDTH， 32
b ChangeBigEndian ;DCD 0xea000007
]
; bigendian ， A A，A+1，A+2，A+3， A，A+1，A+2，A+3
; A A，A+2， A，A+2
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00 b ChangeBigEndian ，
] ; ->
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea b ChangeBigEndian ，
]
|
b ResetHandler ; ENDIAN_CHANGE FALSE ,
]
b HandlerUndef ;handler for Undefined mode ;0x04
b HandlerSWI ;handler for SWI interrupt ;0x08
b HandlerPabort ;handler for PAbort ;0x0c
b HandlerDabort ;handler for DAbort ;0x10
b . ;reserved ;0x14
b HandlerIRQ ;handler for IRQ interrupt ;0x18
b HandlerFIQ ;handler for FIQ interrupt ;0x1c
;@0x20
b EnterPWDN ; Must be @0x20.
;==================================================================================
; , ,
; ,
;==================================================================================
; CP15 C1 7， Bigendian，
ChangeBigEndian ;//here ENTRY_BUS_WIDTH=16
;@0x24
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0
; ， Big-endian
; CPU 32 ， ，CPU ，
; ， CPU
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
; Big-endian ， 16 ，
;
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
;=========================================================================================
; Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON 0x4c00000c
tst r0,#0x8 ; bit[3] SLEEP mode? 1=>sleep
bne ENTER_SLEEP ;C=0, TST 0，bit[3]=1
;// PWDN sleep stop
;// Stop mode
ENTER_STOP
ldr r0,=REFRESH ;0x48000024 DRAM/SDRAM refresh config
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH ;Enable SDRAM self-refresh
str r1, [r0] ;Enable SDRAM self-refresh
mov r1,#16 ;wait until self-refresh is issued. may not be needed.
0
subs r1,r1,#1
bne %B0
;//wait 16 fclks for self-refresh
ldr r0,=CLKCON ;enter STOP mode.
str r2,[r0]
mov r1,#32
0
subs r1,r1,#1 ;1) wait until the STOP mode is in effect.
bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off
;Entering SLEEP mode, only the reset by wake-up is available.
ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
str r3,[r0]
MOV_PC_LR ;back to main process
ENTER_SLEEP
;NOTE.
;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.
ldr r0,=REFRESH
ldr r1,[r0] ;r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh
;//Enable SDRAM self-refresh
mov r1,#16 ;Wait until self-refresh is issued,which may not be needed.
0
subs r1,r1,#1
bne %B0
;//Wait until self-refresh is issued,which may not be needed
ldr r1,=MISCCR ;IO register
ldr r0,[r1]
orr r0,r0,#(7<<17) ;Set SCLK0=1, SCLK1=1, SCKE=1.
str r0,[r1]
ldr r0,=CLKCON ; Enter sleep mode
str r2,[r0]
b . ;CPU will die here.
;// Sleep Mode，1） SDRAM self-refresh
;// 2） MISCCR bit[17] 1:sclk0=sclk 0:sclk0=0
;// bit[18] 1:sclk1=sclk 0:sclk1=0
;// bit[19] 1:Self refresh retain enable
;// 0:Self refresh retain disable
;// When 1, After wake-up from sleep, The self-refresh will be retained.
WAKEUP_SLEEP
;Release SCLKn after wake-up from the SLEEP mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
str r0,[r1]
;// MISCCR
;Set memory control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA
ldr r1,=BWSCON ;BWSCON Address ;//
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4 ; R0 4，[R0]->R3，R0+4->R0
str r3, [r1], #4
cmp r2, r0
bne %B0
;// memory control register， BWSCON，
;// SMRDATA
mov r1,#256
0
subs r1,r1,#1 ;1) wait until the SelfRefresh is released.
bne %B0
;//1) wait until the SelfRefresh is released.
ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up
ldr r0,[r1]
mov pc,r0
;// Sleep Mode， Sleep PC
;============================================================================================
; , HANDLER Hander*** Handle***
LTORG ; , ldr
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
;===================================================================================
; , . , .
; , .
; ??
; ,ARM IRQ FIRQ
; , !
; , !
;===================================================================================
;// ，
;//PC=[HandleEINT0+[INTOFFSET]]
;H|------|
; |/ / / |
; |--isr-| ====>pc
;L|--r8--|
; |--r9--|1 ; Fclk:Hclk 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
; == 243 ==
; If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous
; bus mode using following instructions
;MMU_SetAsyncBusMode
;mrc p15,0,r0,c1,c0,0
;orr r0,r0,#R1_nF:OR:R1_iA
;mcr p15,0,r0,c1,c0,0
[ CLKDIV_VAL>1 ; Fclk:Hclk 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
; UPLL
;//Configure UPLL Fin=12.0MHz UFout=48MHz
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;//USB PLL CONFIG 56,2,2===>48MHz
str r1,[r0]
;7 nop ！！
nop ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
; MPLL
;//Configure MPLL Fin=12.0MHz MFout=304.8MHz
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;68,1,1 ==>304MHz
str r1,[r0]
]
; SLEEP
;//Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2 ;test if bit[1] is 1 or 0 0->C=1
; 1->C=0
;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP ;C=0,jump
EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
;===============================================================================
; , ,
; . SMRDATA ,
;===============================================================================
; SDRAM,flash ROM ,
;SMRDATA map
;SMRDATA memcfg.inc
;Set memory control registers
;ldr r0,=SMRDATA ;dangerous!!!
adrl r0, SMRDATA ;be careful!, tinko
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA ;SMRDATA , 52
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0 ;% ，B -back(F -forward)，0 (0~99)
;================================================================================
; EINT0 ( ), SDRAM ,
;================================================================================
; check if EIN0 button is pressed
ldr r0,=GPFCON
ldr r1,=0x0 ;00 = Input
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff ;1- The pull up function is disabled.
str r1,[r0]
ldr r1,=GPFDAT
ldr r0,[r1]
bic r0,r0,#(0x1e<<1) ; bit clear
tst r0,#0x1
bne %F1 ; , 1 => Initialize stacks
;
ldr r0,=GPFCON
ldr r1,=0x55aa
str r1,[r0]
; ldr r0,=GPFUP
; ldr r1,=0xff
; str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;LED=****
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
ldr r9,=0x4000000 ;64MB
ldr r0,=0x30000000
0
stmia r0!,{r1-r8}
subs r9,r9,#32
bne %B0
; .
;//4.
;Initialize stacks
1
bl InitStacks
;=======================================================================
; , , hzh
; NOR NAND , , .
; NOR NAND .
; , |Image$$RO$$Base|,|Image$$RO$$Limit|... ?
; !!!
;=========================================================================
;BWSCON [2:1] OM[1:0]: OM[1:0] != 00, NOR FLash ； OM[1:0]==00， Nand Flash Mode
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ; #6 == 0110 --> BWSCON[2:1]
bne copy_proc_beg ;OM[1:0] != 00，NOR FLash boot， NAND FLASH
adr r0, ResetEntry ; ,OM[1:0] == 0, NAND FLash
cmp r0, #0 ; 0
; 0 NAND ， 4k 0 stepingstone sram
; adr ， == if use Multi-ice,
bne copy_proc_beg ; !=0, using ice, NAND FLASH. don't read nand flash for boot
;nop
;============== NAND Flash RAM=====================
nand_boot_beg ;
mov r5, #NFCONF ; NAND
;set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID ; NAND ID , r5
mov r6, #0 ;r6 0.
ldr r0, =0xec73 ; NAND ID
cmp r5, r0 ;
beq %F1 ; 1
ldr r0, =0xec75 ;
cmp r5, r0
beq %F1 ; 1
mov r6, #1 ; , r6=1.
1
bl ReadNandStatus ; NAND , r1
mov r8, #0 ; r8 0,
ldr r9, =ResetEntry ; r9
; , ldr , adr , ResetEntry
; , RAM , , |Image$$RO$$Base|
; , RO base RAM ,
; NAND , ldr r9 . ???
2
ands r0, r8, #0x1f ; r8 0x1f(32) -1,eq ,ne
bne %F3 ; (32 ) --
mov r0, r8 ;r8->r0
bl CheckBadBlk ; NAND
cmp r0, #0 ; r0 0
addne r8, r8, #32 ; : + 32 . : r8 = blockpage addr， ( 512Byte)
bne %F4 ; 4 。 3 copy
3
mov r0, r8 ; ->r0
mov r1, r9 ; ->r1
bl ReadNandPage ; NAND RAM
add r9, r9, #512 ; 512Bytes
add r8, r8, #1 ;r8
4
cmp r8, #256 ; 256 128KBytes
; ： 128KByte (by Tinko)
bcc %B2 ; r8 256( ), 2
; now copy completed
mov r5, #NFCONF ;Disable NandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]
ldr pc, =copy_proc_beg ; copy_proc_beg
; InitRam ?????????????????????????????
;===========================================================
copy_proc_beg
adrl r0, ResetEntry ;ResetEntry ->r0
; ， adr， ldr。 ldr ResetEntry ，
; 。 adr ResetEntry ， 。
; stepingstone ， ResetEntry 。 RAM ， ResetEntry ＲＡＭ
; ， RO base。
ldr r2, BaseOfROM ;BaseOfROM ( )->r2
cmp r0, r2 ; ResetEntry BaseOfROM
ldreq r0, TopOfROM ; ( --- ice -- code ro ， code rw ),TopOfROM->r0
beq InitRam ; InitRam
; ， code RO
;=========================================================
; NOR FLASH
; ResetEntry ,TopOfROM-BaseOfROM BaseOfROM
;TopOfROM BaseOfROM |Image$$RO$$Limit| |Image$$RO$$Base|
;|Image$$RO$$Limit| |Image$$RO$$Base|
;
;BaseOfBSS BaseOfZero |Image$$RW$$Base| |Image$$ZI$$Base|
;|Image$$RW$$Base| |Image$$ZI$$Base|
;
; -- ， ZI --
;=======================================================
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7} ; ，r0 = ResetEntry --- source
stmia r2!, {r4-r7} ; ，r2 = BaseOfROM --- destination
cmp r2, r3 ; ： TopOfROM-BaseOfROM
bcc %B0
;---------------------------------------------------------------
; 2 ， ， tinko
; " ! "， 。
;---------------------------------------------------------------
adrl r0, ResetEntry ;don't use adr, 'cause out of range error occures
ldr r2, BaseOfROM
; RW
; 2 r0（ code rw ）
sub r2, r2, r3 ;r2=BaseOfROM-TopOfROM=(-)
sub r0, r0, r2 ;r0=ResetEntry-(-) =ResetEntry+
InitRam
; RM |Image$$RW$$Base|
ldr r2, BaseOfBSS ;BaseOfBSS->r2 , BaseOfBSS = |Image$$RW$$Base|
ldr r3, BaseOfZero ;BaseOfZero->r3 , BaseOfZero = |Image$$ZI$$Base|
0
cmp r2, r3 ; BaseOfBSS BaseOfZero
ldrcc r1, [r0], #4 ; ，r0( ) = TopOfROM. BaseOfZero-BaseOfBSS code， BaseOfBSS
strcc r1, [r2], #4
bcc %B0
; 0 ZI
mov r0, #0
ldr r3, EndOfBSS ;EndOfBSS = |Image$$ZI$$Limit|
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
; r21 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
;bl Led_Test
;===========================================================
; C ,
; ( ) .
;//5.
; Setup IRQ handler
ldr r0,=HandleIRQ ;This routine is needed
ldr r1,=IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
;//initialize the IRQ HandleIRQ
;//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
; ， !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;//6. ram C main bootloader
;If main() is used, the variable initialization will be done in __main().
[ {FALSE} ;by tinko -- tinko ，
[ :LNOT:USE_MAIN ;initialized {FALSE}
;Copy and paste RW data/zero initialized data
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different just for debug??????????????????????????
BEQ %F2
1
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
BCC %B1
2
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
3
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %B3
]
]
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;***************************************
;by tinko
[ {TRUE} ; , LED
;rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
; Led_Display
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0xe0
str r1,[r0]
ldr r2, =0xffffffff;
1
sub r2,r2,#1
bne %b1
ldr r0,=GPFDAT
ldr r1,=0xe0
;b . ;die here
]
;*****************************************
;*****************************************************************************
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
; , !!!!!!!!!!
; C main .
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;*****************************************************************************
[ :LNOT:THUMBCODE ;if thumbcode={false} bl main L logic
bl Main ;Don't use main() because ......
b . ;
]
;//if thumbcod={ture}
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Don't use main() because ......
b . ;
CODE32
]
;function initializing stacks
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;// user stacks， ？
mov pc,lr
;The LR register won't be valid if the current mode is not SVC mode.？
;// SVCmode？
;===========================================================
ReadNandID
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x90 ;WrNFCmd(RdIDCMD);
strb r0,[r7,#8]
mov r4,#0 ;WrNFAddr(0);
strb r4,[r7,#0xc]
1 ;while(NFIsBusy());
ldr r0,[r7,#0x20]
tst r0,#1
beq %B1
ldrb r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0x10] ;id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
ReadNandStatus
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
strb r0,[r7,#8]
ldrb r1,[r7,#0x10] ;r1 = RdNFDat();
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
WaitNandBusy
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
mov r1,#NFCONF
strb r0,[r1,#8]
1 ;while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0x10]
tst r0,#0x40
beq %B1
mov r0,#0 ;WrNFCmd(READCMD0);
strb r0,[r1,#8]
mov pc,lr
CheckBadBlk
mov r7, lr
mov r5, #NFCONF
bic r0,r0,#0x1f ;addr &= ~0x1f;
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0x50 ;WrNFCmd(READCMD2)
strb r1,[r5,#8]
mov r1, #5;6 ;6->5
strb r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne %B1
2
ldr r0, [r5, #0x20]
tst r0, #1
beq %B2
ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
ldr r1,[r5,#4] ;NFChipDs()
orr r1,r1,#2
str r1,[r5,#4]
mov pc, r7
ReadNandPage
mov r7,lr
mov r4,r1
mov r5,#NFCONF
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
strb r1,[r5,#0xc] ;WrNFAddr(0)
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
ldr r0,[r5,#4] ;InitEcc()
orr r0,r0,#0x10
str r0,[r5,#4]
bl WaitNandBusy ;WaitNFBusy()
mov r0,#0 ;for(i=0; i<512; i++)
1
ldrb r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
bic r0,r0,#0x10000
cmp r0,#0x200
bcc %B1
ldr r0,[r5,#4] ;NFChipDs()
orr r0,r0,#2
str r0,[r5,#4]
mov pc,r7
;--------------------LED test
EXPORT Led_Test
Led_Test
mov r0, #0x56000000
mov r1, #0x5500
str r1, [r0, #0x50]
0
mov r1, #0x50
str r1, [r0, #0x54]
mov r2, #0x100000
1
subs r2, r2, #1
bne %B1
mov r1, #0xa0
str r1, [r0, #0x54]
mov r2, #0x100000
2
subs r2, r2, #1
bne %B2
b %B0
mov pc, lr
;===========================================================
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144
CLKDIV124
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKDIV144
ldr r0, = CLKDIVN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
;
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+ (B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+ (B6_BWSCON<<24)+(B7_BWSCON<<28)) ; bank bus width; B0， OM[1:0]pins
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6 B6_MT memcfg.inc ，11-->SDRAM ; B6_SCAN - reset
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;Tchr- not used
;DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x31 ;SCLK power saving mode, BANKSIZE 64M/64M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END ==================================================
; C ,
; ( ) .
;//5.
; Setup IRQ handler
ldr r0,=HandleIRQ ;This routine is needed
ldr r1,=IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
;//initialize the IRQ HandleIRQ
;//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
; ， !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;//6. ram C main bootloader
;If main() is used, the variable initialization will be done in __main().
[ {FALSE} ;by tinko -- tinko ，
[ :LNOT:USE_MAIN ;initialized {FALSE}
;Copy and paste RW data/zero initialized data
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different just for debug??????????????????????????
BEQ %F2
1
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
BCC %B1
2
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
3
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %B3
]
]
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;***************************************
;by tinko
[ {TRUE} ; , LED
;rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
; Led_Display
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0xe0
str r1,[r0]
ldr r2, =0xffffffff;
1
sub r2,r2,#1
bne %b1
ldr r0,=GPFDAT
ldr r1,=0xe0
;b . ;die here
]
;*****************************************
;*****************************************************************************
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
; , !!!!!!!!!!
; C main .
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;*****************************************************************************
[ :LNOT:THUMBCODE ;if thumbcode={false} bl main L logic
bl Main ;Don't use main() because ......
b . ;
]
;//if thumbcod={ture}
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Don't use main() because ......
b . ;
CODE32
]
;function initializing stacks
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;// user stacks， ？
mov pc,lr
;The LR register won't be valid if the current mode is not SVC mode.？
;// SVCmode？
;===========================================================
ReadNandID
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x90 ;WrNFCmd(RdIDCMD);
strb r0,[r7,#8]
mov r4,#0 ;WrNFAddr(0);
strb r4,[r7,#0xc]
1 ;while(NFIsBusy());
ldr r0,[r7,#0x20]
tst r0,#1
beq %B1
ldrb r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0x10] ;id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
ReadNandStatus
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
strb r0,[r7,#8]
ldrb r1,[r7,#0x10] ;r1 = RdNFDat();
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
WaitNandBusy
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
mov r1,#NFCONF
strb r0,[r1,#8]
1 ;while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0x10]
tst r0,#0x40
beq %B1
mov r0,#0 ;WrNFCmd(READCMD0);
strb r0,[r1,#8]
mov pc,lr
CheckBadBlk
mov r7, lr
mov r5, #NFCONF
bic r0,r0,#0x1f ;addr &= ~0x1f;
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0x50 ;WrNFCmd(READCMD2)
strb r1,[r5,#8]
mov r1, #5;6 ;6->5
strb r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne %B1
2
ldr r0, [r5, #0x20]
tst r0, #1
beq %B2
ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
ldr r1,[r5,#4] ;NFChipDs()
orr r1,r1,#2
str r1,[r5,#4]
mov pc, r7
ReadNandPage
mov r7,lr
mov r4,r1
mov r5,#NFCONF
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
strb r1,[r5,#0xc] ;WrNFAddr(0)
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
ldr r0,[r5,#4] ;InitEcc()
orr r0,r0,#0x10
str r0,[r5,#4]
bl WaitNandBusy ;WaitNFBusy()
mov r0,#0 ;for(i=0; i<512; i++)
1
ldrb r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
bic r0,r0,#0x10000
cmp r0,#0x200
bcc %B1
ldr r0,[r5,#4] ;NFChipDs()
orr r0,r0,#2
str r0,[r5,#4]
mov pc,r7
;--------------------LED test
EXPORT Led_Test
Led_Test
mov r0, #0x56000000
mov r1, #0x5500
str r1, [r0, #0x50]
0
mov r1, #0x50
str r1, [r0, #0x54]
mov r2, #0x100000
1
subs r2, r2, #1
bne %B1
mov r1, #0xa0
str r1, [r0, #0x54]
mov r2, #0x100000
2
subs r2, r2, #1
bne %B2
b %B0
mov pc, lr
;===========================================================
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144
CLKDIV124
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKDIV144
ldr r0, = CLKDIVN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
;
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+ (B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+ (B6_BWSCON<<24)+(B7_BWSCON<<28)) ; bank bus width; B0， OM[1:0]pins
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6 B6_MT memcfg.inc ，11-->SDRAM ; B6_SCAN - reset
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;Tchr- not used
;DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x31 ;SCLK power saving mode, BANKSIZE 64M/64M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4;=========================================
; NAME: 2440INIT.S
; DESC: C start up codes
; Configure memory, ISR ,stacks
; Initialize C-variables
;
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode
; 2003.03.14:DonGo: Modified for 2440.
; 2009 06.24:Tinko Modified
;=========================================
; include ， Get
; *.h ， *.inc
GET option.inc ;
GET memcfg.inc ;
GET 2440addr.inc ;
;REFRESH [22]bit : 0- auto refresh; 1 - self refresh
BIT_SELFREFRESH EQU (1<<22) ; ，SDRAM
; : CPSR 5 M[4:0]
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f ;M[4:0]
NOINT EQU 0xc0
;
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ _STACK_BASEADDRESS option.inc
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
;arm 1.arm:32 arm 2.Thumb:16
; Thumb
; 16 32 16 32
;
;code16 16 thumb
;code32 32 arm
;
;Arm ARM ， ARM Thumb ， ARM ， init.s
; 。 ， THUMBCODE ， main
;
;
; （16 tasm.exe
;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE ; THUMBCODE EQU
[ {CONFIG} = 16 ; 16 （ thumb ）
THUMBCODE SETL {TRUE} ; THUMBCODE TURE
CODE32 ; ARM ，
| ;（| else） ARM
THUMBCODE SETL {FALSE} ; THUMBCODE FALSE
] ;
MACRO ; THUMBCODE PC LR
MOV_PC_LR ;
[ THUMBCODE ; THUMBCODE，
bx lr ; ARM BX THUMB , . bx PC 1 thumb
| ; ，
mov pc,lr ; ARM
]
MEND ;
MACRO ; ,
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr
|
moveq pc,lr
]
MEND
;=======================================================================================
; ,
; _ISR_STARTADDRESS=0x33FF_FF00 Handle*** .
; ENTRY ( ) b Handler*** .
; Handler*** HANDLER Handle*** .
; , ENTRY ROM(FLASH) ,
; , .
;========================================================================================
;; pc ， “ ”。
; （ ），34 ， 。
; ， Handle*** 。
; “ ” 。
;
; cpu 0x18 IRQ ， ;
; 0x18 ，
; ADC 0xC0, 0xC0
; ：ldr PC,=HandlerADC ADC
; HandlerADC
; ， ， interrupt
;pending 0x18
; interrupt pending
;
;
;H|------| H|------| H|------| H|------| H|------|
; |/ / / | |/ / / | |/ / / | |/ / / | |/ / / |
; |------|pc
; | | | | |--r0--|r0
; (0) (1) (2) (3) (4)
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel ;
sub sp,sp,#4 ;(1) sp( )
stmfd sp!,{r0} ;(2) (lr does not push because it return to original address)
ldr r0,=$HandleLabel; HandleXXX r0
ldr r0,[r0] ; HandleXXX ( ) r0
str r0,[sp,#4] ;(3) (ISR)
ldmfd sp!,{r0,pc} ;(4) r0 pc ( ISR )
MEND
;=========================================================================================
; IMPORT ( c extren ) |Image$$RO$$Base|,|Image$$RO$$Limit|...
; ADS RO Base RW Base ,
; .
; ,
;==========================================================================================
;Image$$RO$$Base 。RO, RW, ZI Flash ， RW，ZI Flash
; ， Flash RW，ZI RAM 。
; ， 。 main() ， b __Main, __Main
; Main ， RW，ZI 。 b Main， 。
; RO，RW，ZI ， RW，ZI Flash ，
; RW，ZI Flash RO 。 Image$$RO$$Base，Image$$RO$$Limit， Image$$RO$$Limit
; RW（ROM data） 。
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
; , main
;IMPORT MMU_SetAsyncBusMode
;IMPORT MMU_SetFastBusMode ;hzh
IMPORT Main
; !
AREA Init,CODE,READONLY ; Init
ENTRY ; ( )
EXPORT __ENTRY ; _ENTRY,
__ENTRY
ResetEntry
;1)The code, which converts to Big-endian, should be in little endian code.
;2)The following little endian code will be compiled in Big-Endian mode.
; The code byte order should be changed as the memory bus width.
;3)The pseudo instruction,DCD can not be used here because the linker generates error.
; ，
ASSERT :DEF:ENDIAN_CHANGE ; ENDIAN_CHANGE
[ ENDIAN_CHANGE ; ENDIAN_CHANGE， （ Option.inc FALSE ）
ASSERT :DEF:ENTRY_BUS_WIDTH ; ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32 ; ENTRY_BUS_WIDTH， 32
b ChangeBigEndian ;DCD 0xea000007
]
; bigendian ， A A，A+1，A+2，A+3， A，A+1，A+2，A+3
; A A，A+2， A，A+2
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00 b ChangeBigEndian ，
] ; ->
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea b ChangeBigEndian ，
]
|
b ResetHandler ; ENDIAN_CHANGE FALSE ,
]
b HandlerUndef ;handler for Undefined mode ;0x04
b HandlerSWI ;handler for SWI interrupt ;0x08
b HandlerPabort ;handler for PAbort ;0x0c
b HandlerDabort ;handler for DAbort ;0x10
b . ;reserved ;0x14
b HandlerIRQ ;handler for IRQ interrupt ;0x18
b HandlerFIQ ;handler for FIQ interrupt ;0x1c
;@0x20
b EnterPWDN ; Must be @0x20.
;==================================================================================
; , ,
; ,
;==================================================================================
; CP15 C1 7， Bigendian，
ChangeBigEndian ;//here ENTRY_BUS_WIDTH=16
;@0x24
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0
; ， Big-endian
; CPU 32 ， ，CPU ，
; ， CPU
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
; Big-endian ， 16 ，
;
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
;=========================================================================================
; Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON 0x4c00000c
tst r0,#0x8 ; bit[3] SLEEP mode? 1=>sleep
bne ENTER_SLEEP ;C=0, TST 0，bit[3]=1
;// PWDN sleep stop
;// Stop mode
ENTER_STOP
ldr r0,=REFRESH ;0x48000024 DRAM/SDRAM refresh config
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH ;Enable SDRAM self-refresh
str r1, [r0] ;Enable SDRAM self-refresh
mov r1,#16 ;wait until self-refresh is issued. may not be needed.
0
subs r1,r1,#1
bne %B0
;//wait 16 fclks for self-refresh
ldr r0,=CLKCON ;enter STOP mode.
str r2,[r0]
mov r1,#32
0
subs r1,r1,#1 ;1) wait until the STOP mode is in effect.
bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off
;Entering SLEEP mode, only the reset by wake-up is available.
ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
str r3,[r0]
MOV_PC_LR ;back to main process
ENTER_SLEEP
;NOTE.
;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.
ldr r0,=REFRESH
ldr r1,[r0] ;r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh
;//Enable SDRAM self-refresh
mov r1,#16 ;Wait until self-refresh is issued,which may not be needed.
0
subs r1,r1,#1
bne %B0
;//Wait until self-refresh is issued,which may not be needed
ldr r1,=MISCCR ;IO register
ldr r0,[r1]
orr r0,r0,#(7<<17) ;Set SCLK0=1, SCLK1=1, SCKE=1.
str r0,[r1]
ldr r0,=CLKCON ; Enter sleep mode
str r2,[r0]
b . ;CPU will die here.
;// Sleep Mode，1） SDRAM self-refresh
;// 2） MISCCR bit[17] 1:sclk0=sclk 0:sclk0=0
;// bit[18] 1:sclk1=sclk 0:sclk1=0
;// bit[19] 1:Self refresh retain enable
;// 0:Self refresh retain disable
;// When 1, After wake-up from sleep, The self-refresh will be retained.
WAKEUP_SLEEP
;Release SCLKn after wake-up from the SLEEP mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
str r0,[r1]
;// MISCCR
;Set memory control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA
ldr r1,=BWSCON ;BWSCON Address ;//
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4 ; R0 4，[R0]->R3，R0+4->R0
str r3, [r1], #4
cmp r2, r0
bne %B0
;// memory control register， BWSCON，
;// SMRDATA
mov r1,#256
0
subs r1,r1,#1 ;1) wait until the SelfRefresh is released.
bne %B0
;//1) wait until the SelfRefresh is released.
ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up
ldr r0,[r1]
mov pc,r0
;// Sleep Mode， Sleep PC
;============================================================================================
; , HANDLER Hander*** Handle***
LTORG ; , ldr
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
;===================================================================================
; , . , .
; , .
; ??
; ,ARM IRQ FIRQ
; , !
; , !
;===================================================================================
;// ，
;//PC=[HandleEINT0+[INTOFFSET]]
;H|------|
; |/ / / |
; |--isr-| ====>pc
;L|--r8--|
; |--r9--|1 ; Fclk:Hclk 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
; == 243 ==
; If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous
; bus mode using following instructions
;MMU_SetAsyncBusMode
;mrc p15,0,r0,c1,c0,0
;orr r0,r0,#R1_nF:OR:R1_iA
;mcr p15,0,r0,c1,c0,0
[ CLKDIV_VAL>1 ; Fclk:Hclk 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
; UPLL
;//Configure UPLL Fin=12.0MHz UFout=48MHz
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;//USB PLL CONFIG 56,2,2===>48MHz
str r1,[r0]
;7 nop ！！
nop ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
; MPLL
;//Configure MPLL Fin=12.0MHz MFout=304.8MHz
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;68,1,1 ==>304MHz
str r1,[r0]
]
; SLEEP
;//Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2 ;test if bit[1] is 1 or 0 0->C=1
; 1->C=0
;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP ;C=0,jump
EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
;===============================================================================
; , ,
; . SMRDATA ,
;===============================================================================
; SDRAM,flash ROM ,
;SMRDATA map
;SMRDATA memcfg.inc
;Set memory control registers
;ldr r0,=SMRDATA ;dangerous!!!
adrl r0, SMRDATA ;be careful!, tinko
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA ;SMRDATA , 52
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0 ;% ，B -back(F -forward)，0 (0~99)
;================================================================================
; EINT0 ( ), SDRAM ,
;================================================================================
; check if EIN0 button is pressed
ldr r0,=GPFCON
ldr r1,=0x0 ;00 = Input
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff ;1- The pull up function is disabled.
str r1,[r0]
ldr r1,=GPFDAT
ldr r0,[r1]
bic r0,r0,#(0x1e<<1) ; bit clear
tst r0,#0x1
bne %F1 ; , 1 => Initialize stacks
;
ldr r0,=GPFCON
ldr r1,=0x55aa
str r1,[r0]
; ldr r0,=GPFUP
; ldr r1,=0xff
; str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;LED=****
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
ldr r9,=0x4000000 ;64MB
ldr r0,=0x30000000
0
stmia r0!,{r1-r8}
subs r9,r9,#32
bne %B0
; .
;//4.
;Initialize stacks
1
bl InitStacks
;=======================================================================
; , , hzh
; NOR NAND , , .
; NOR NAND .
; , |Image$$RO$$Base|,|Image$$RO$$Limit|... ?
; !!!
;=========================================================================
;BWSCON [2:1] OM[1:0]: OM[1:0] != 00, NOR FLash ； OM[1:0]==00， Nand Flash Mode
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ; #6 == 0110 --> BWSCON[2:1]
bne copy_proc_beg ;OM[1:0] != 00，NOR FLash boot， NAND FLASH
adr r0, ResetEntry ; ,OM[1:0] == 0, NAND FLash
cmp r0, #0 ; 0
; 0 NAND ， 4k 0 stepingstone sram
; adr ， == if use Multi-ice,
bne copy_proc_beg ; !=0, using ice, NAND FLASH. don't read nand flash for boot
;nop
;============== NAND Flash RAM=====================
nand_boot_beg ;
mov r5, #NFCONF ; NAND
;set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID ; NAND ID , r5
mov r6, #0 ;r6 0.
ldr r0, =0xec73 ; NAND ID
cmp r5, r0 ;
beq %F1 ; 1
ldr r0, =0xec75 ;
cmp r5, r0
beq %F1 ; 1
mov r6, #1 ; , r6=1.
1
bl ReadNandStatus ; NAND , r1
mov r8, #0 ; r8 0,
ldr r9, =ResetEntry ; r9
; , ldr , adr , ResetEntry
; , RAM , , |Image$$RO$$Base|
; , RO base RAM ,
; NAND , ldr r9 . ???
2
ands r0, r8, #0x1f ; r8 0x1f(32) -1,eq ,ne
bne %F3 ; (32 ) --
mov r0, r8 ;r8->r0
bl CheckBadBlk ; NAND
cmp r0, #0 ; r0 0
addne r8, r8, #32 ; : + 32 . : r8 = blockpage addr， ( 512Byte)
bne %F4 ; 4 。 3 copy
3
mov r0, r8 ; ->r0
mov r1, r9 ; ->r1
bl ReadNandPage ; NAND RAM
add r9, r9, #512 ; 512Bytes
add r8, r8, #1 ;r8
4
cmp r8, #256 ; 256 128KBytes
; ： 128KByte (by Tinko)
bcc %B2 ; r8 256( ), 2
; now copy completed
mov r5, #NFCONF ;Disable NandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]
ldr pc, =copy_proc_beg ; copy_proc_beg
; InitRam ?????????????????????????????
;===========================================================
copy_proc_beg
adrl r0, ResetEntry ;ResetEntry ->r0
; ， adr， ldr。 ldr ResetEntry ，
; 。 adr ResetEntry ， 。
; stepingstone ， ResetEntry 。 RAM ， ResetEntry ＲＡＭ
; ， RO base。
ldr r2, BaseOfROM ;BaseOfROM ( )->r2
cmp r0, r2 ; ResetEntry BaseOfROM
ldreq r0, TopOfROM ; ( --- ice -- code ro ， code rw ),TopOfROM->r0
beq InitRam ; InitRam
; ， code RO
;=========================================================
; NOR FLASH
; ResetEntry ,TopOfROM-BaseOfROM BaseOfROM
;TopOfROM BaseOfROM |Image$$RO$$Limit| |Image$$RO$$Base|
;|Image$$RO$$Limit| |Image$$RO$$Base|
;
;BaseOfBSS BaseOfZero |Image$$RW$$Base| |Image$$ZI$$Base|
;|Image$$RW$$Base| |Image$$ZI$$Base|
;
; -- ， ZI --
;=======================================================
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7} ; ，r0 = ResetEntry --- source
stmia r2!, {r4-r7} ; ，r2 = BaseOfROM --- destination
cmp r2, r3 ; ： TopOfROM-BaseOfROM
bcc %B0
;---------------------------------------------------------------
; 2 ， ， tinko
; " ! "， 。
;---------------------------------------------------------------
adrl r0, ResetEntry ;don't use adr, 'cause out of range error occures
ldr r2, BaseOfROM
; RW
; 2 r0（ code rw ）
sub r2, r2, r3 ;r2=BaseOfROM-TopOfROM=(-)
sub r0, r0, r2 ;r0=ResetEntry-(-) =ResetEntry+
InitRam
; RM |Image$$RW$$Base|
ldr r2, BaseOfBSS ;BaseOfBSS->r2 , BaseOfBSS = |Image$$RW$$Base|
ldr r3, BaseOfZero ;BaseOfZero->r3 , BaseOfZero = |Image$$ZI$$Base|
0
cmp r2, r3 ; BaseOfBSS BaseOfZero
ldrcc r1, [r0], #4 ; ，r0( ) = TopOfROM. BaseOfZero-BaseOfBSS code， BaseOfBSS
strcc r1, [r2], #4
bcc %B0
; 0 ZI
mov r0, #0
ldr r3, EndOfBSS ;EndOfBSS = |Image$$ZI$$Limit|
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
; r21 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
;bl Led_Test
;===========================================================
; C ,
; ( ) .
;//5.
; Setup IRQ handler
ldr r0,=HandleIRQ ;This routine is needed
ldr r1,=IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
;//initialize the IRQ HandleIRQ
;//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
; ， !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;//6. ram C main bootloader
;If main() is used, the variable initialization will be done in __main().
[ {FALSE} ;by tinko -- tinko ，
[ :LNOT:USE_MAIN ;initialized {FALSE}
;Copy and paste RW data/zero initialized data
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different just for debug??????????????????????????
BEQ %F2
1
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
BCC %B1
2
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
3
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %B3
]
]
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;***************************************
;by tinko
[ {TRUE} ; , LED
;rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
; Led_Display
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0xe0
str r1,[r0]
ldr r2, =0xffffffff;
1
sub r2,r2,#1
bne %b1
ldr r0,=GPFDAT
ldr r1,=0xe0
;b . ;die here
]
;*****************************************
;*****************************************************************************
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
; , !!!!!!!!!!
; C main .
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;*****************************************************************************
[ :LNOT:THUMBCODE ;if thumbcode={false} bl main L logic
bl Main ;Don't use main() because ......
b . ;
]
;//if thumbcod={ture}
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Don't use main() because ......
b . ;
CODE32
]
;function initializing stacks
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;// user stacks， ？
mov pc,lr
;The LR register won't be valid if the current mode is not SVC mode.？
;// SVCmode？
;===========================================================
ReadNandID
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x90 ;WrNFCmd(RdIDCMD);
strb r0,[r7,#8]
mov r4,#0 ;WrNFAddr(0);
strb r4,[r7,#0xc]
1 ;while(NFIsBusy());
ldr r0,[r7,#0x20]
tst r0,#1
beq %B1
ldrb r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0x10] ;id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
ReadNandStatus
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
strb r0,[r7,#8]
ldrb r1,[r7,#0x10] ;r1 = RdNFDat();
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
WaitNandBusy
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
mov r1,#NFCONF
strb r0,[r1,#8]
1 ;while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0x10]
tst r0,#0x40
beq %B1
mov r0,#0 ;WrNFCmd(READCMD0);
strb r0,[r1,#8]
mov pc,lr
CheckBadBlk
mov r7, lr
mov r5, #NFCONF
bic r0,r0,#0x1f ;addr &= ~0x1f;
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0x50 ;WrNFCmd(READCMD2)
strb r1,[r5,#8]
mov r1, #5;6 ;6->5
strb r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne %B1
2
ldr r0, [r5, #0x20]
tst r0, #1
beq %B2
ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
ldr r1,[r5,#4] ;NFChipDs()
orr r1,r1,#2
str r1,[r5,#4]
mov pc, r7
ReadNandPage
mov r7,lr
mov r4,r1
mov r5,#NFCONF
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
strb r1,[r5,#0xc] ;WrNFAddr(0)
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
ldr r0,[r5,#4] ;InitEcc()
orr r0,r0,#0x10
str r0,[r5,#4]
bl WaitNandBusy ;WaitNFBusy()
mov r0,#0 ;for(i=0; i<512; i++)
1
ldrb r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
bic r0,r0,#0x10000
cmp r0,#0x200
bcc %B1
ldr r0,[r5,#4] ;NFChipDs()
orr r0,r0,#2
str r0,[r5,#4]
mov pc,r7
;--------------------LED test
EXPORT Led_Test
Led_Test
mov r0, #0x56000000
mov r1, #0x5500
str r1, [r0, #0x50]
0
mov r1, #0x50
str r1, [r0, #0x54]
mov r2, #0x100000
1
subs r2, r2, #1
bne %B1
mov r1, #0xa0
str r1, [r0, #0x54]
mov r2, #0x100000
2
subs r2, r2, #1
bne %B2
b %B0
mov pc, lr
;===========================================================
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144
CLKDIV124
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKDIV144
ldr r0, = CLKDIVN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
;
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+ (B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+ (B6_BWSCON<<24)+(B7_BWSCON<<28)) ; bank bus width; B0， OM[1:0]pins
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6 B6_MT memcfg.inc ，11-->SDRAM ; B6_SCAN - reset
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;Tchr- not used
;DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x31 ;SCLK power saving mode, BANKSIZE 64M/64M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END =======================================
; NAME: 2440INIT.S
; DESC: C start up codes
; Configure memory, ISR ,stacks
; Initialize C-variables
;
; HISTORY:
; 2002.02.25:kwtark: ver 0.0
; 2002.03.20:purnnamu: Add some functions for testing STOP,Sleep mode
; 2003.03.14:DonGo: Modified for 2440.
; 2009 06.24:Tinko Modified
;=========================================
; include ， Get
; *.h ， *.inc
GET option.inc ;
GET memcfg.inc ;
GET 2440addr.inc ;
;REFRESH [22]bit : 0- auto refresh; 1 - self refresh
BIT_SELFREFRESH EQU (1<<22) ; ，SDRAM
; : CPSR 5 M[4:0]
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f ;M[4:0]
NOINT EQU 0xc0
;
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~ _STACK_BASEADDRESS option.inc
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
;arm 1.arm:32 arm 2.Thumb:16
; Thumb
; 16 32 16 32
;
;code16 16 thumb
;code32 32 arm
;
;Arm ARM ， ARM Thumb ， ARM ， init.s
; 。 ， THUMBCODE ， main
;
;
; （16 tasm.exe
;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE ; THUMBCODE EQU
[ {CONFIG} = 16 ; 16 （ thumb ）
THUMBCODE SETL {TRUE} ; THUMBCODE TURE
CODE32 ; ARM ，
| ;（| else） ARM
THUMBCODE SETL {FALSE} ; THUMBCODE FALSE
] ;
MACRO ; THUMBCODE PC LR
MOV_PC_LR ;
[ THUMBCODE ; THUMBCODE，
bx lr ; ARM BX THUMB , . bx PC 1 thumb
| ; ，
mov pc,lr ; ARM
]
MEND ;
MACRO ; ,
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr
|
moveq pc,lr
]
MEND
;=======================================================================================
; ,
; _ISR_STARTADDRESS=0x33FF_FF00 Handle*** .
; ENTRY ( ) b Handler*** .
; Handler*** HANDLER Handle*** .
; , ENTRY ROM(FLASH) ,
; , .
;========================================================================================
;; pc ， “ ”。
; （ ），34 ， 。
; ， Handle*** 。
; “ ” 。
;
; cpu 0x18 IRQ ， ;
; 0x18 ，
; ADC 0xC0, 0xC0
; ：ldr PC,=HandlerADC ADC
; HandlerADC
; ， ， interrupt
;pending 0x18
; interrupt pending
;
;
;H|------| H|------| H|------| H|------| H|------|
; |/ / / | |/ / / | |/ / / | |/ / / | |/ / / |
; |------|pc
; | | | | |--r0--|r0
; (0) (1) (2) (3) (4)
MACRO
$HandlerLabel HANDLER $HandleLabel
$HandlerLabel ;
sub sp,sp,#4 ;(1) sp( )
stmfd sp!,{r0} ;(2) (lr does not push because it return to original address)
ldr r0,=$HandleLabel; HandleXXX r0
ldr r0,[r0] ; HandleXXX ( ) r0
str r0,[sp,#4] ;(3) (ISR)
ldmfd sp!,{r0,pc} ;(4) r0 pc ( ISR )
MEND
;=========================================================================================
; IMPORT ( c extren ) |Image$$RO$$Base|,|Image$$RO$$Limit|...
; ADS RO Base RW Base ,
; .
; ,
;==========================================================================================
;Image$$RO$$Base 。RO, RW, ZI Flash ， RW，ZI Flash
; ， Flash RW，ZI RAM 。
; ， 。 main() ， b __Main, __Main
; Main ， RW，ZI 。 b Main， 。
; RO，RW，ZI ， RW，ZI Flash ，
; RW，ZI Flash RO 。 Image$$RO$$Base，Image$$RO$$Limit， Image$$RO$$Limit
; RW（ROM data） 。
IMPORT |Image$$RO$$Base| ; Base of ROM code
IMPORT |Image$$RO$$Limit| ; End of ROM code (=start of ROM data)
IMPORT |Image$$RW$$Base| ; Base of RAM to initialise
IMPORT |Image$$ZI$$Base| ; Base and limit of area
IMPORT |Image$$ZI$$Limit| ; to zero initialise
; , main
;IMPORT MMU_SetAsyncBusMode
;IMPORT MMU_SetFastBusMode ;hzh
IMPORT Main
; !
AREA Init,CODE,READONLY ; Init
ENTRY ; ( )
EXPORT __ENTRY ; _ENTRY,
__ENTRY
ResetEntry
;1)The code, which converts to Big-endian, should be in little endian code.
;2)The following little endian code will be compiled in Big-Endian mode.
; The code byte order should be changed as the memory bus width.
;3)The pseudo instruction,DCD can not be used here because the linker generates error.
; ，
ASSERT :DEF:ENDIAN_CHANGE ; ENDIAN_CHANGE
[ ENDIAN_CHANGE ; ENDIAN_CHANGE， （ Option.inc FALSE ）
ASSERT :DEF:ENTRY_BUS_WIDTH ; ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32 ; ENTRY_BUS_WIDTH， 32
b ChangeBigEndian ;DCD 0xea000007
]
; bigendian ， A A，A+1，A+2，A+3， A，A+1，A+2，A+3
; A A，A+2， A，A+2
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00 b ChangeBigEndian ，
] ; ->
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea b ChangeBigEndian ，
]
|
b ResetHandler ; ENDIAN_CHANGE FALSE ,
]
b HandlerUndef ;handler for Undefined mode ;0x04
b HandlerSWI ;handler for SWI interrupt ;0x08
b HandlerPabort ;handler for PAbort ;0x0c
b HandlerDabort ;handler for DAbort ;0x10
b . ;reserved ;0x14
b HandlerIRQ ;handler for IRQ interrupt ;0x18
b HandlerFIQ ;handler for FIQ interrupt ;0x1c
;@0x20
b EnterPWDN ; Must be @0x20.
;==================================================================================
; , ,
; ,
;==================================================================================
; CP15 C1 7， Bigendian，
ChangeBigEndian ;//here ENTRY_BUS_WIDTH=16
;@0x24
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0
; ， Big-endian
; CPU 32 ， ，CPU ，
; ， CPU
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
; Big-endian ， 16 ，
;
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b ResetHandler
;=========================================================================================
; Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON 0x4c00000c
tst r0,#0x8 ; bit[3] SLEEP mode? 1=>sleep
bne ENTER_SLEEP ;C=0, TST 0，bit[3]=1
;// PWDN sleep stop
;// Stop mode
ENTER_STOP
ldr r0,=REFRESH ;0x48000024 DRAM/SDRAM refresh config
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH ;Enable SDRAM self-refresh
str r1, [r0] ;Enable SDRAM self-refresh
mov r1,#16 ;wait until self-refresh is issued. may not be needed.
0
subs r1,r1,#1
bne %B0
;//wait 16 fclks for self-refresh
ldr r0,=CLKCON ;enter STOP mode.
str r2,[r0]
mov r1,#32
0
subs r1,r1,#1 ;1) wait until the STOP mode is in effect.
bne %B0 ;2) Or wait here until the CPU&Peripherals will be turned-off
;Entering SLEEP mode, only the reset by wake-up is available.
ldr r0,=REFRESH ;exit from SDRAM self refresh mode.
str r3,[r0]
MOV_PC_LR ;back to main process
ENTER_SLEEP
;NOTE.
;1) rGSTATUS3 should have the return address after wake-up from SLEEP mode.
ldr r0,=REFRESH
ldr r1,[r0] ;r1=rREFRESH
orr r1, r1, #BIT_SELFREFRESH
str r1, [r0] ;Enable SDRAM self-refresh
;//Enable SDRAM self-refresh
mov r1,#16 ;Wait until self-refresh is issued,which may not be needed.
0
subs r1,r1,#1
bne %B0
;//Wait until self-refresh is issued,which may not be needed
ldr r1,=MISCCR ;IO register
ldr r0,[r1]
orr r0,r0,#(7<<17) ;Set SCLK0=1, SCLK1=1, SCKE=1.
str r0,[r1]
ldr r0,=CLKCON ; Enter sleep mode
str r2,[r0]
b . ;CPU will die here.
;// Sleep Mode，1） SDRAM self-refresh
;// 2） MISCCR bit[17] 1:sclk0=sclk 0:sclk0=0
;// bit[18] 1:sclk1=sclk 0:sclk1=0
;// bit[19] 1:Self refresh retain enable
;// 0:Self refresh retain disable
;// When 1, After wake-up from sleep, The self-refresh will be retained.
WAKEUP_SLEEP
;Release SCLKn after wake-up from the SLEEP mode.
ldr r1,=MISCCR
ldr r0,[r1]
bic r0,r0,#(7<<17) ;SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:0->=SCKE.
str r0,[r1]
;// MISCCR
;Set memory control registers
;ldr r0,=SMRDATA
adrl r0, SMRDATA
ldr r1,=BWSCON ;BWSCON Address ;//
add r2, r0, #52 ;End address of SMRDATA
0
ldr r3, [r0], #4 ; R0 4，[R0]->R3，R0+4->R0
str r3, [r1], #4
cmp r2, r0
bne %B0
;// memory control register， BWSCON，
;// SMRDATA
mov r1,#256
0
subs r1,r1,#1 ;1) wait until the SelfRefresh is released.
bne %B0
;//1) wait until the SelfRefresh is released.
ldr r1,=GSTATUS3 ;GSTATUS3 has the start address just after SLEEP wake-up
ldr r0,[r1]
mov pc,r0
;// Sleep Mode， Sleep PC
;============================================================================================
; , HANDLER Hander*** Handle***
LTORG ; , ldr
HandlerFIQ HANDLER HandleFIQ
HandlerIRQ HANDLER HandleIRQ
HandlerUndef HANDLER HandleUndef
HandlerSWI HANDLER HandleSWI
HandlerDabort HANDLER HandleDabort
HandlerPabort HANDLER HandlePabort
;===================================================================================
; , . , .
; , .
; ??
; ,ARM IRQ FIRQ
; , !
; , !
;===================================================================================
;// ，
;//PC=[HandleEINT0+[INTOFFSET]]
;H|------|
; |/ / / |
; |--isr-| ====>pc
;L|--r8--|
; |--r9--|1 ; Fclk:Hclk 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
; == 243 ==
; If HDIVN is not 0, the CPU bus mode has to be changed from the fast bus mode to the asynchronous
; bus mode using following instructions
;MMU_SetAsyncBusMode
;mrc p15,0,r0,c1,c0,0
;orr r0,r0,#R1_nF:OR:R1_iA
;mcr p15,0,r0,c1,c0,0
[ CLKDIV_VAL>1 ; Fclk:Hclk 1:1.
mrc p15,0,r0,c1,c0,0
orr r0,r0,#0xc0000000;R1_nF:OR:R1_iA
mcr p15,0,r0,c1,c0,0
|
mrc p15,0,r0,c1,c0,0
bic r0,r0,#0xc0000000;R1_iA:OR:R1_nF
mcr p15,0,r0,c1,c0,0
]
; UPLL
;//Configure UPLL Fin=12.0MHz UFout=48MHz
ldr r0,=UPLLCON
ldr r1,=((U_MDIV<<12)+(U_PDIV<<4)+U_SDIV) ;//USB PLL CONFIG 56,2,2===>48MHz
str r1,[r0]
;7 nop ！！
nop ;// Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
; MPLL
;//Configure MPLL Fin=12.0MHz MFout=304.8MHz
ldr r0,=MPLLCON
ldr r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV) ;68,1,1 ==>304MHz
str r1,[r0]
]
; SLEEP
;//Check if the boot is caused by the wake-up from SLEEP mode.
ldr r1,=GSTATUS2
ldr r0,[r1]
tst r0,#0x2 ;test if bit[1] is 1 or 0 0->C=1
; 1->C=0
;In case of the wake-up from SLEEP mode, go to SLEEP_WAKEUP handler.
bne WAKEUP_SLEEP ;C=0,jump
EXPORT StartPointAfterSleepWakeUp
StartPointAfterSleepWakeUp
;===============================================================================
; , ,
; . SMRDATA ,
;===============================================================================
; SDRAM,flash ROM ,
;SMRDATA map
;SMRDATA memcfg.inc
;Set memory control registers
;ldr r0,=SMRDATA ;dangerous!!!
adrl r0, SMRDATA ;be careful!, tinko
ldr r1,=BWSCON ;BWSCON Address
add r2, r0, #52 ;End address of SMRDATA ;SMRDATA , 52
0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B0 ;% ，B -back(F -forward)，0 (0~99)
;================================================================================
; EINT0 ( ), SDRAM ,
;================================================================================
; check if EIN0 button is pressed
ldr r0,=GPFCON
ldr r1,=0x0 ;00 = Input
str r1,[r0]
ldr r0,=GPFUP
ldr r1,=0xff ;1- The pull up function is disabled.
str r1,[r0]
ldr r1,=GPFDAT
ldr r0,[r1]
bic r0,r0,#(0x1e<<1) ; bit clear
tst r0,#0x1
bne %F1 ; , 1 => Initialize stacks
;
ldr r0,=GPFCON
ldr r1,=0x55aa
str r1,[r0]
; ldr r0,=GPFUP
; ldr r1,=0xff
; str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x0
str r1,[r0] ;LED=****
mov r1,#0
mov r2,#0
mov r3,#0
mov r4,#0
mov r5,#0
mov r6,#0
mov r7,#0
mov r8,#0
ldr r9,=0x4000000 ;64MB
ldr r0,=0x30000000
0
stmia r0!,{r1-r8}
subs r9,r9,#32
bne %B0
; .
;//4.
;Initialize stacks
1
bl InitStacks
;=======================================================================
; , , hzh
; NOR NAND , , .
; NOR NAND .
; , |Image$$RO$$Base|,|Image$$RO$$Limit|... ?
; !!!
;=========================================================================
;BWSCON [2:1] OM[1:0]: OM[1:0] != 00, NOR FLash ； OM[1:0]==00， Nand Flash Mode
ldr r0, =BWSCON
ldr r0, [r0]
ands r0, r0, #6 ; #6 == 0110 --> BWSCON[2:1]
bne copy_proc_beg ;OM[1:0] != 00，NOR FLash boot， NAND FLASH
adr r0, ResetEntry ; ,OM[1:0] == 0, NAND FLash
cmp r0, #0 ; 0
; 0 NAND ， 4k 0 stepingstone sram
; adr ， == if use Multi-ice,
bne copy_proc_beg ; !=0, using ice, NAND FLASH. don't read nand flash for boot
;nop
;============== NAND Flash RAM=====================
nand_boot_beg ;
mov r5, #NFCONF ; NAND
;set timing value
ldr r0, =(7<<12)|(7<<8)|(7<<4)
str r0, [r5]
;enable control
ldr r0, =(0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)
str r0, [r5, #4]
bl ReadNandID ; NAND ID , r5
mov r6, #0 ;r6 0.
ldr r0, =0xec73 ; NAND ID
cmp r5, r0 ;
beq %F1 ; 1
ldr r0, =0xec75 ;
cmp r5, r0
beq %F1 ; 1
mov r6, #1 ; , r6=1.
1
bl ReadNandStatus ; NAND , r1
mov r8, #0 ; r8 0,
ldr r9, =ResetEntry ; r9
; , ldr , adr , ResetEntry
; , RAM , , |Image$$RO$$Base|
; , RO base RAM ,
; NAND , ldr r9 . ???
2
ands r0, r8, #0x1f ; r8 0x1f(32) -1,eq ,ne
bne %F3 ; (32 ) --
mov r0, r8 ;r8->r0
bl CheckBadBlk ; NAND
cmp r0, #0 ; r0 0
addne r8, r8, #32 ; : + 32 . : r8 = blockpage addr， ( 512Byte)
bne %F4 ; 4 。 3 copy
3
mov r0, r8 ; ->r0
mov r1, r9 ; ->r1
bl ReadNandPage ; NAND RAM
add r9, r9, #512 ; 512Bytes
add r8, r8, #1 ;r8
4
cmp r8, #256 ; 256 128KBytes
; ： 128KByte (by Tinko)
bcc %B2 ; r8 256( ), 2
; now copy completed
mov r5, #NFCONF ;Disable NandFlash
ldr r0, [r5, #4]
bic r0, r0, #1
str r0, [r5, #4]
ldr pc, =copy_proc_beg ; copy_proc_beg
; InitRam ?????????????????????????????
;===========================================================
copy_proc_beg
adrl r0, ResetEntry ;ResetEntry ->r0
; ， adr， ldr。 ldr ResetEntry ，
; 。 adr ResetEntry ， 。
; stepingstone ， ResetEntry 。 RAM ， ResetEntry ＲＡＭ
; ， RO base。
ldr r2, BaseOfROM ;BaseOfROM ( )->r2
cmp r0, r2 ; ResetEntry BaseOfROM
ldreq r0, TopOfROM ; ( --- ice -- code ro ， code rw ),TopOfROM->r0
beq InitRam ; InitRam
; ， code RO
;=========================================================
; NOR FLASH
; ResetEntry ,TopOfROM-BaseOfROM BaseOfROM
;TopOfROM BaseOfROM |Image$$RO$$Limit| |Image$$RO$$Base|
;|Image$$RO$$Limit| |Image$$RO$$Base|
;
;BaseOfBSS BaseOfZero |Image$$RW$$Base| |Image$$ZI$$Base|
;|Image$$RW$$Base| |Image$$ZI$$Base|
;
; -- ， ZI --
;=======================================================
ldr r3, TopOfROM
0
ldmia r0!, {r4-r7} ; ，r0 = ResetEntry --- source
stmia r2!, {r4-r7} ; ，r2 = BaseOfROM --- destination
cmp r2, r3 ; ： TopOfROM-BaseOfROM
bcc %B0
;---------------------------------------------------------------
; 2 ， ， tinko
; " ! "， 。
;---------------------------------------------------------------
adrl r0, ResetEntry ;don't use adr, 'cause out of range error occures
ldr r2, BaseOfROM
; RW
; 2 r0（ code rw ）
sub r2, r2, r3 ;r2=BaseOfROM-TopOfROM=(-)
sub r0, r0, r2 ;r0=ResetEntry-(-) =ResetEntry+
InitRam
; RM |Image$$RW$$Base|
ldr r2, BaseOfBSS ;BaseOfBSS->r2 , BaseOfBSS = |Image$$RW$$Base|
ldr r3, BaseOfZero ;BaseOfZero->r3 , BaseOfZero = |Image$$ZI$$Base|
0
cmp r2, r3 ; BaseOfBSS BaseOfZero
ldrcc r1, [r0], #4 ; ，r0( ) = TopOfROM. BaseOfZero-BaseOfBSS code， BaseOfBSS
strcc r1, [r2], #4
bcc %B0
; 0 ZI
mov r0, #0
ldr r3, EndOfBSS ;EndOfBSS = |Image$$ZI$$Limit|
1
cmp r2, r3
strcc r0, [r2], #4
bcc %B1
; r21 ; means Fclk:Hclk is not 1:1.
; bl MMU_SetAsyncBusMode
; |
; bl MMU_SetFastBusMode ; default value.
; ]
;bl Led_Test
;===========================================================
; C ,
; ( ) .
;//5.
; Setup IRQ handler
ldr r0,=HandleIRQ ;This routine is needed
ldr r1,=IsrIRQ ;if there isn't 'subs pc,lr,#4' at 0x18, 0x1c
str r1,[r0]
;//initialize the IRQ HandleIRQ
;//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
; ， !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;//6. ram C main bootloader
;If main() is used, the variable initialization will be done in __main().
[ {FALSE} ;by tinko -- tinko ，
[ :LNOT:USE_MAIN ;initialized {FALSE}
;Copy and paste RW data/zero initialized data
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
LDR r1, =|Image$$RW$$Base| ; and RAM copy
LDR r3, =|Image$$ZI$$Base|
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different just for debug??????????????????????????
BEQ %F2
1
CMP r1, r3 ; Copy init data
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] + ADD r0, r0, #4
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] + ADD r1, r1, #4
BCC %B1
2
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
3
CMP r3, r1 ; Zero init
STRCC r2, [r3], #4
BCC %B3
]
]
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;***************************************
;by tinko
[ {TRUE} ; , LED
;rGPFDAT = (rGPFDAT & ~(0xf<<4)) | ((~data & 0xf)<<4);
; Led_Display
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0xe0
str r1,[r0]
ldr r2, =0xffffffff;
1
sub r2,r2,#1
bne %b1
ldr r0,=GPFDAT
ldr r1,=0xe0
;b . ;die here
]
;*****************************************
;*****************************************************************************
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
; , !!!!!!!!!!
; C main .
;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
;*****************************************************************************
[ :LNOT:THUMBCODE ;if thumbcode={false} bl main L logic
bl Main ;Don't use main() because ......
b . ;
]
;//if thumbcod={ture}
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Don't use main() because ......
b . ;
CODE32
]
;function initializing stacks
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
mrs r0,cpsr
bic r0,r0,#MODEMASK
orr r1,r0,#UNDEFMODE|NOINT
msr cpsr_cxsf,r1 ;UndefMode
ldr sp,=UndefStack ; UndefStack=0x33FF_5C00
orr r1,r0,#ABORTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=AbortStack ; AbortStack=0x33FF_6000
orr r1,r0,#IRQMODE|NOINT
msr cpsr_cxsf,r1 ;IRQMode
ldr sp,=IRQStack ; IRQStack=0x33FF_7000
orr r1,r0,#FIQMODE|NOINT
msr cpsr_cxsf,r1 ;FIQMode
ldr sp,=FIQStack ; FIQStack=0x33FF_8000
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack ; SVCStack=0x33FF_5800
;USER mode has not be initialized.
;// user stacks， ？
mov pc,lr
;The LR register won't be valid if the current mode is not SVC mode.？
;// SVCmode？
;===========================================================
ReadNandID
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x90 ;WrNFCmd(RdIDCMD);
strb r0,[r7,#8]
mov r4,#0 ;WrNFAddr(0);
strb r4,[r7,#0xc]
1 ;while(NFIsBusy());
ldr r0,[r7,#0x20]
tst r0,#1
beq %B1
ldrb r0,[r7,#0x10] ;id = RdNFDat()<<8;
mov r0,r0,lsl #8
ldrb r1,[r7,#0x10] ;id |= RdNFDat();
orr r5,r1,r0
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
ReadNandStatus
mov r7,#NFCONF
ldr r0,[r7,#4] ;NFChipEn();
bic r0,r0,#2
str r0,[r7,#4]
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
strb r0,[r7,#8]
ldrb r1,[r7,#0x10] ;r1 = RdNFDat();
ldr r0,[r7,#4] ;NFChipDs();
orr r0,r0,#2
str r0,[r7,#4]
mov pc,lr
WaitNandBusy
mov r0,#0x70 ;WrNFCmd(QUERYCMD);
mov r1,#NFCONF
strb r0,[r1,#8]
1 ;while(!(RdNFDat()&0x40));
ldrb r0,[r1,#0x10]
tst r0,#0x40
beq %B1
mov r0,#0 ;WrNFCmd(READCMD0);
strb r0,[r1,#8]
mov pc,lr
CheckBadBlk
mov r7, lr
mov r5, #NFCONF
bic r0,r0,#0x1f ;addr &= ~0x1f;
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0x50 ;WrNFCmd(READCMD2)
strb r1,[r5,#8]
mov r1, #5;6 ;6->5
strb r1,[r5,#0xc] ;WrNFAddr(5);(6) 6->5
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
; bl WaitNandBusy ;WaitNFBusy()
;do not use WaitNandBusy, after WaitNandBusy will read part A!
mov r0, #100
1
subs r0, r0, #1
bne %B1
2
ldr r0, [r5, #0x20]
tst r0, #1
beq %B2
ldrb r0, [r5,#0x10] ;RdNFDat()
sub r0, r0, #0xff
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
ldr r1,[r5,#4] ;NFChipDs()
orr r1,r1,#2
str r1,[r5,#4]
mov pc, r7
ReadNandPage
mov r7,lr
mov r4,r1
mov r5,#NFCONF
ldr r1,[r5,#4] ;NFChipEn()
bic r1,r1,#2
str r1,[r5,#4]
mov r1,#0 ;WrNFCmd(READCMD0)
strb r1,[r5,#8]
strb r1,[r5,#0xc] ;WrNFAddr(0)
strb r0,[r5,#0xc] ;WrNFAddr(addr)
mov r1,r0,lsr #8 ;WrNFAddr(addr>>8)
strb r1,[r5,#0xc]
cmp r6,#0 ;if(NandAddr)
movne r0,r0,lsr #16 ;WrNFAddr(addr>>16)
strneb r0,[r5,#0xc]
ldr r0,[r5,#4] ;InitEcc()
orr r0,r0,#0x10
str r0,[r5,#4]
bl WaitNandBusy ;WaitNFBusy()
mov r0,#0 ;for(i=0; i<512; i++)
1
ldrb r1,[r5,#0x10] ;buf[i] = RdNFDat()
strb r1,[r4,r0]
add r0,r0,#1
bic r0,r0,#0x10000
cmp r0,#0x200
bcc %B1
ldr r0,[r5,#4] ;NFChipDs()
orr r0,r0,#2
str r0,[r5,#4]
mov pc,r7
;--------------------LED test
EXPORT Led_Test
Led_Test
mov r0, #0x56000000
mov r1, #0x5500
str r1, [r0, #0x50]
0
mov r1, #0x50
str r1, [r0, #0x54]
mov r2, #0x100000
1
subs r2, r2, #1
bne %B1
mov r1, #0xa0
str r1, [r0, #0x54]
mov r2, #0x100000
2
subs r2, r2, #1
bne %B2
b %B0
mov pc, lr
;===========================================================
;=====================================================================
; Clock division test
; Assemble code, because VSYNC time is very short
;=====================================================================
EXPORT CLKDIV124
EXPORT CLKDIV144
CLKDIV124
ldr r0, = CLKDIVN
ldr r1, = 0x3 ; 0x3 = 1:2:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x470 ; REFCNT135
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
CLKDIV144
ldr r0, = CLKDIVN
ldr r1, = 0x4 ; 0x4 = 1:4:4
str r1, [r0]
; wait until clock is stable
nop
nop
nop
nop
nop
ldr r0, = REFRESH
ldr r1, [r0]
bic r1, r1, #0xff
bic r1, r1, #(0x7<<8)
orr r1, r1, #0x630 ; REFCNT675 - 1520
str r1, [r0]
nop
nop
nop
nop
nop
mov pc, lr
;
LTORG
SMRDATA DATA
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
; 1) The memory settings is safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK<=75Mhz.
DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+ (B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+ (B6_BWSCON<<24)+(B7_BWSCON<<28)) ; bank bus width; B0， OM[1:0]pins
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6 B6_MT memcfg.inc ，11-->SDRAM ; B6_SCAN - reset
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;Tchr- not used
;DCD 0x32 ;SCLK power saving mode, BANKSIZE 128M/128M
DCD 0x31 ;SCLK power saving mode, BANKSIZE 64M/64M
DCD 0x30 ;MRSR6 CL=3clk
DCD 0x30 ;MRSR7 CL=3clk
BaseOfROM DCD |Image$$RO$$Base|
TopOfROM DCD |Image$$RO$$Limit|
BaseOfBSS DCD |Image$$RW$$Base|
BaseOfZero DCD |Image$$ZI$$Base|
EndOfBSS DCD |Image$$ZI$$Limit|
ALIGN
AREA RamData, DATA, READWRITE
^ _ISR_STARTADDRESS ; _ISR_STARTADDRESS=0x33FF_FF00
HandleReset # 4
HandleUndef # 4
HandleSWI # 4
HandlePabort # 4
HandleDabort # 4
HandleReserved # 4
HandleIRQ # 4
HandleFIQ # 4
;Don't use the label 'IntVectorTable',
;The value of IntVectorTable is different with the address you think it may be.
;IntVectorTable
;@0x33FF_FF20
HandleEINT0 # 4
HandleEINT1 # 4
HandleEINT2 # 4
HandleEINT3 # 4
HandleEINT4_7 # 4
HandleEINT8_23 # 4
HandleCAM # 4 ; Added for 2440.
HandleBATFLT # 4
HandleTICK # 4
HandleWDT # 4
HandleTIMER0 # 4
HandleTIMER1 # 4
HandleTIMER2 # 4
HandleTIMER3 # 4
HandleTIMER4 # 4
HandleUART2 # 4
;@0x33FF_FF60
HandleLCD # 4
HandleDMA0 # 4
HandleDMA1 # 4
HandleDMA2 # 4
HandleDMA3 # 4
HandleMMC # 4
HandleSPI0 # 4
HandleUART1 # 4
HandleNFCON # 4 ; Added for 2440.
HandleUSBD # 4
HandleUSBH # 4
HandleIIC # 4
HandleUART0 # 4
HandleSPI1 # 4
HandleRTC # 4
HandleADC # 4
;@0x33FF_FFA0
END