module test1(input clk, input rst, output tx);
    localparam NEXT = 4'b0;
    localparam DONE = 4'b1111;
    reg [1:0] mod3;
    reg [2:0] mod5;
    reg [7:0] char;
    reg [3:0] state = NEXT;
    reg [3:0] dg2 = 0,
        dg1 = 0,
        dg0 = 0;
    wire ed;
    reg send = 0;
    reg [23:0] cnt;
    wire clk2 = cnt[13];
    tx1 tx1(.clk(clk), .rst(rst), .send(send), .data(char), .tx(tx), .ed(ed));
    always @(posedge clk)
    begin   
        cnt <= cnt + 1'b1;
    end 
    always @(posedge clk2)
    begin   
    send <= 0;  
        if (ed)
        begin

            if (!rst)
            begin
                mod3 <= 2'd0;
                mod5 <= 3'd0;
                state <= NEXT;
                dg2 <= 0;
                dg1 <= 0;
                dg0 <= 0;
            end
            else if (state == NEXT)
            begin               
                if (dg2 == 1 && dg1 == 0 && dg0 == 0)
                begin
                    state <= DONE;
                end
                else
                begin
                    if (dg0 != 4'd9)
                    begin
                        dg0 <= dg0 + 1'b1;
                    end
                    else
                    begin
                        dg0 <= 4'd0;
                        if (dg1 != 4'd9)
                        begin
                            dg1 <= dg1 + 1'b1;
                        end
                        else
                        begin
                            dg1 <= 4'd0;
                            dg2 <= dg2 + 1'b1;
                        end
                    end
                    mod3 <= (mod3 == 2) ? 0 : mod3 + 1;
                    mod5 <= (mod5 == 4) ? 0 : mod5 + 1;
                    state <= 1;
                end
            end
            else if (state != DONE)
            begin
                state <= state + 1;
                if (mod3 == 0 && mod5 == 0)
                begin
                    case (state)
                    1:
                        char <= "F";
                    2:
                        char <= "I";
                    3:
                        char <= "Z";
                    4:
                        char <= "Z";
                    5:
                        char <= "B";
                    6:
                        char <= "U";
                    7:
                        char <= "Z";
                    8:
                        char <= "Z";
                    9:
                    begin
                        char <= " ";
                        state <= NEXT;
                    end
                    endcase
                end
                else if (mod3 == 0)
                begin
                    case (state)
                    1:
                        char <= "F";
                    2:
                        char <= "I";
                    3:
                        char <= "Z";
                    4:
                        char <= "Z";
                    5:
                    begin
                        char <= " ";
                        state <= NEXT;
                    end
                    endcase
                end
                else if (mod5 == 0)
                begin
                    case (state)
                    1:
                        char <= "B";
                    2:
                        char <= "U";
                    3:
                        char <= "Z";
                    4:
                        char <= "Z";
                    5:
                    begin
                        char <= " ";
                        state <= NEXT;
                    end
                    endcase
                end
                else
                begin
                    case (state)
                    1:
                    begin
                        if (dg2 == 0)
                        begin
                            char <= " ";
                        end
                        else
                        begin
                            char <= {2'b11, dg2[3:0]};
                        end
                    end
                    2:
                    begin
                        if (dg2 == 0 && dg1 == 0)
                        begin
                            char <= " ";
                        end
                        else
                        begin
                            char <= {2'b11, dg1[3:0]};
                        end
                    end
                    3:
                    begin
                        char <= {2'b11, dg0[3:0]};
                    end
                    4:
                    begin
                        char <= " ";
                        state <= NEXT;
                    end
                    endcase
                end
                send <= 1;
            end
        end
    end
endmodule