vistaでquartus その21

5513 ワード
FPGA quartus Polyphony FPGA テキストリンク

概要

vistaでquartusやってみた。
7seg led、光らせてみた。
polyphonyで書いてみた。
0を表示してみた。

環境

windows vista 32bit
quartus ii v13.0
polyphony v0.3.6
ep2c5t144ボード
qyf-tm1638ボード

写真

接続

vcc -- 5v 
dio -- pin25
clk -- pin24
stb -- pin8
gnd -- gnd

サンプルコード

from polyphony import module, testbench, is_worker_running
from polyphony.io import Port
from polyphony.typing import bit, bit8
from polyphony.timing import clksleep, clkfence, wait_value

@module
class boss:
    def __init__(self):
        self.busy = Port(bit, 'in')
        self.stb = Port(bit, 'out', 1)
        self.start = Port(bit, 'out', 0)
        self.data = Port(bit8, 'out', 1)
        self.h = [0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00]
        self.append_worker(self.main_worker)
    def main_worker(self):
        i = 0
        while is_worker_running():
            self.start.wr(0)
            if (i < 1):
                wait_value(0, self.busy)
                self.start.wr(0)
                self.stb.wr(1)

                self.data(0x88)
                self.stb.wr(0)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)
                self.stb.wr(1)

                self.data(0x40)
                self.stb.wr(0)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)
                self.stb.wr(1)

                self.data(0xc0)
                self.stb.wr(0)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[0])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[1])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[2])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[3])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[4])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[5])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[6])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(self.h[7])
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.start.wr(0)

                self.data(0x01)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.stb.wr(1)
                self.start.wr(0)

                self.data(0x88)
                self.stb.wr(0)
                self.start.wr(1)
                clksleep(3)
                wait_value(0, self.busy)
                self.stb.wr(1)
                self.start.wr(0)
                i = i + 1

m = boss()

@testbench
def test(m):
    m.busy.wr(0)
    for i in range(20):
        wait_value(1, m.start)
        m.busy.wr(1)
        data = m.data.rd()
        print(data)
        m.busy.wr(0)

test(m)

以上。