MTKにETTテストコードを入れる
50806 ワード
ハードウェアはETTをテストする必要があるため、テストを保証するためにセグメントcodeを追加する必要があります.
1、preloaderにコードを入れてエラーを報告し、plのサイズがramのサイズを超えているため、印刷メッセージを削除する必要がある.
2、kernelにettテストのコードを入れる
3、diffファイルをETTに保存する.diff.
4、patch方式でこのpatchを入れる:
このpatch:patch-p 1 5、ETT.diffファイル具体的には、以下のコードをコピーし、ファイル名をETTと命名する.diff:
1、preloaderにコードを入れてエラーを報告し、plのサイズがramのサイズを超えているため、印刷メッセージを削除する必要がある.
2、kernelにettテストのコードを入れる
3、diffファイルをETTに保存する.diff.
4、patch方式でこのpatchを入れる:
このpatch:patch-p 1
diff --git a/bootable/bootloader/preloader/platform/mt6735/src/drivers/emi.c b/bootable/bootloader/preloader/platform/mt6735/src/drivers/emi.c
index 374e8bd..d8df37f 100644
--- a/bootable/bootloader/preloader/platform/mt6735/src/drivers/emi.c
+++ b/bootable/bootloader/preloader/platform/mt6735/src/drivers/emi.c
@@ -43,6 +43,7 @@
#include <emi_hw.h>
#include <stdlib.h>
#include <upmu_hw.h>
+#include "dramc.h" //ETT test
#ifdef COMBO_MCP
#include "custom_emi.h"
@@ -3438,13 +3439,13 @@ void pmic_voltage_read(unsigned int nAdjust)
unsigned int OldVcore1 = 0;
unsigned int OldVmem = 0, OldVmem1 = 0;
- printf("[PMIC]pmic_voltage_read : \r
");
+ print("[PMIC]pmic_voltage_read : \r
");
ret_val = pmic_read_interface(MT6328_VCORE1_CON11, &OldVcore1, 0x7F, 0);
ret_val = pmic_read_interface(MT6328_SLDO_ANA_CON0, &OldVmem, 0x7F, 0);
ret_val = pmic_read_interface(MT6328_SLDO_ANA_CON1, &OldVmem1, 0x0F, 8);
- printf("[Vcore] MT6328_VCORE1_CON11=0x%x,\r
[Vmem] MT6328_SLDO_ANA_CON0/1=0x%x 0x%x\r
", OldVcore1, OldVmem, OldVmem1);
+ print("[Vcore] MT6328_VCORE1_CON11=0x%x,\r
[Vmem] MT6328_SLDO_ANA_CON0/1=0x%x 0x%x\r
", OldVcore1, OldVmem, OldVmem1);
}
void pmic_force_PWM_Mode(void)
@@ -3453,7 +3454,7 @@ void pmic_force_PWM_Mode(void)
pmic_config_interface(MT6328_VCORE_ANA_CON1, 0x01, 0x01, 11);
pmic_read_interface(MT6328_VCORE_ANA_CON1, &vcore1_pwm, 0x1FFF, 0);
- printf("[Vcore] MT6328_VCORE_ANA_CON1 = 0x%x
", vcore1_pwm);
+ print("[Vcore] MT6328_VCORE_ANA_CON1 = 0x%x
", vcore1_pwm);
}
void pmic_Vcore_adjust(int nAdjust)
diff --git a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc1.h b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc1.h
index 1447f5e..06f4668 100644
--- a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc1.h
+++ b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc1.h
@@ -112,7 +112,7 @@
//#define CUSTOM_CONFIG_MAX_DRAM_SIZE 0x3F000000
//#define ENABLE_SYNC_MASK
-//#define pmic_HQA_TCs
+#define pmic_HQA_TCs
//#define WAVEFORM_MEASURE
//#define DRAM_INIT_CYCLES
diff --git a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc2.h b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc2.h
index d70f65c..71d6dfa 100644
--- a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc2.h
+++ b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc2.h
@@ -112,7 +112,7 @@
//#define CUSTOM_CONFIG_MAX_DRAM_SIZE 0x3F000000
//#define ENABLE_SYNC_MASK
-//#define pmic_HQA_TCs
+#define pmic_HQA_TCs
//#define WAVEFORM_MEASURE
//#define DRAM_INIT_CYCLES
diff --git a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc3.h b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc3.h
index 79bacce..d0ca825 100644
--- a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc3.h
+++ b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/dramc3.h
@@ -113,7 +113,7 @@
//#define CUSTOM_CONFIG_MAX_DRAM_SIZE 0x3F000000
//#define ENABLE_SYNC_MASK
-//#define pmic_HQA_TCs
+#define pmic_HQA_TCs
//#define WAVEFORM_MEASURE
//#define DRAM_INIT_CYCLES
diff --git a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/pmic_wrap_init.h b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/pmic_wrap_init.h
index 93664cd..e382a51 100644
--- a/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/pmic_wrap_init.h
+++ b/bootable/bootloader/preloader/platform/mt6735/src/drivers/inc/pmic_wrap_init.h
@@ -15,7 +15,7 @@
#define PWRAPFUC(fmt, arg...) printf(PWRAPTAG "%s
", __FUNCTION__)
#endif
#define PWRAPLOG(fmt, arg...) printf(PWRAPTAG fmt,##arg)
-#define PWRAPERR(fmt, arg...) printf(PWRAPTAG "ERROR,line=%d " fmt, __LINE__, ##arg)
+#define PWRAPERR(fmt, arg...) printf(PWRAPTAG "ERROR,line=%d " __LINE__)
#define PWRAPREG(fmt, arg...) printf(PWRAPTAG fmt,##arg)
diff --git a/bootable/bootloader/preloader/platform/mt6735/src/drivers/platform.c b/bootable/bootloader/preloader/platform/mt6735/src/drivers/platform.c
index b9e26af..527c1cc 100644
--- a/bootable/bootloader/preloader/platform/mt6735/src/drivers/platform.c
+++ b/bootable/bootloader/preloader/platform/mt6735/src/drivers/platform.c
@@ -60,6 +60,7 @@
#include "spm_mtcmos.h"
#include "mt_ptp.h"
#include "clkbuf_ctl.h"
+#include "dramc.h" //ETT test
/*============================================================================*/
/* CONSTAND DEFINITIONS */
/*============================================================================*/
@@ -109,7 +110,7 @@ void platform_core_handler(void)
if (0 == aarch64_slt_done())
{
- print("
%s in platform_core_handler
", MOD);
+ //print("
%s in platform_core_handler
", MOD);
for (i = NR_CPUS - 1; i > 0; --i)
spm_mtcmos_ctrl_cpu(i, STA_POWER_ON, 0);
@@ -163,7 +164,7 @@ int usb_cable_in(void)
if ((g_boot_reason == BR_USB) || usb_accessory_in()) {
ret = mt_charger_type_detection();
if (ret == STANDARD_HOST || ret == CHARGING_HOST) {
- print("
%s USB cable in
", MOD);
+ ////print("
%s USB cable in
", MOD);
mt_usb_phy_poweron();
mt_usb_phy_savecurrent();
@@ -177,7 +178,7 @@ int usb_cable_in(void)
return exist;
#else
- print("
%s USB cable in
", MOD);
+ ////print("
%s USB cable in
", MOD);
mt_usb_phy_poweron();
mt_usb_phy_savecurrent();
@@ -191,7 +192,7 @@ void show_tx(void)
UINT8 var;
USBPHY_I2C_READ8(0x6E, &var);
UINT8 var2 = (var >> 3) & ~0xFE;
- print("[USB]addr: 0x6E (TX), value: %x - %x
", var, var2);
+ ////print("[USB]addr: 0x6E (TX), value: %x - %x
", var, var2);
}
void store_tx(UINT8 value)
@@ -210,7 +211,7 @@ void store_tx(UINT8 value)
USBPHY_I2C_READ8(0x6E, &var);
var2 = (var >> 3) & ~0xFE;
- print("[USB]addr: 0x6E TX [AFTER WRITE], value after: %x - %x
", var, var2);
+ ////print("[USB]addr: 0x6E TX [AFTER WRITE], value after: %x - %x
", var, var2);
}
void show_rx(void)
@@ -218,7 +219,7 @@ void show_rx(void)
UINT8 var;
USBPHY_I2C_READ8(0x77, &var);
UINT8 var2 = (var >> 7) & ~0xFE;
- print("[USB]addr: 0x77 (RX) [AFTER WRITE], value after: %x - %x
", var, var2);
+ ////print("[USB]addr: 0x77 (RX) [AFTER WRITE], value after: %x - %x
", var, var2);
}
void test_uart(void)
@@ -248,47 +249,47 @@ void set_to_usb_mode(void)
#if !CFG_FPGA_PLATFORM
/* Turn on USB MCU Bus Clock */
var = READ_REG(PERI_GLOBALCON_PDN0_SET);
- print("
[USB]USB bus clock: 0x008, value: %x
", var);
+ //print("
[USB]USB bus clock: 0x008, value: %x
", var);
USB_CLR_BIT(USB0_PDN, PERI_GLOBALCON_PDN0_SET);
var = READ_REG(PERI_GLOBALCON_PDN0_SET);
- print("
[USB]USB bus clock: 0x008, value after: %x
", var);
+ //print("
[USB]USB bus clock: 0x008, value after: %x
", var);
/* Switch from BC1.1 mode to USB mode */
var = USBPHY_READ8(0x1A);
- print("
[USB]addr: 0x1A, value: %x
", var);
+ //print("
[USB]addr: 0x1A, value: %x
", var);
USBPHY_WRITE8(0x1A, var & 0x7f);
- print("
[USB]addr: 0x1A, value after: %x
", USBPHY_READ8(0x1A));
+ //print("
[USB]addr: 0x1A, value after: %x
", USBPHY_READ8(0x1A));
/* Set RG_UART_EN to 0 */
var = USBPHY_READ8(0x6E);
- print("
[USB]addr: 0x6E, value: %x
", var);
+ //print("
[USB]addr: 0x6E, value: %x
", var);
USBPHY_WRITE8(0x6E, var & ~0x01);
- print("
[USB]addr: 0x6E, value after: %x
", USBPHY_READ8(0x6E));
+ //print("
[USB]addr: 0x6E, value after: %x
", USBPHY_READ8(0x6E));
/* Set RG_USB20_DM_100K_EN to 0 */
var = USBPHY_READ8(0x22);
- print("
[USB]addr: 0x22, value: %x
", var);
+ //print("
[USB]addr: 0x22, value: %x
", var);
USBPHY_WRITE8(0x22, var & ~0x02);
- print("
[USB]addr: 0x22, value after: %x
", USBPHY_READ8(0x22));
+ //print("
[USB]addr: 0x22, value after: %x
", USBPHY_READ8(0x22));
#else
/* Set RG_UART_EN to 0 */
USBPHY_I2C_READ8(0x6E, &var);
- print("
[USB]addr: 0x6E, value: %x
", var);
+ //print("
[USB]addr: 0x6E, value: %x
", var);
USBPHY_I2C_WRITE8(0x6E, var & ~0x01);
USBPHY_I2C_READ8(0x6E, &var);
- print("
[USB]addr: 0x6E, value after: %x
", var);
+ //print("
[USB]addr: 0x6E, value after: %x
", var);
/* Set RG_USB20_DM_100K_EN to 0 */
USBPHY_I2C_READ8(0x22, &var);
- print("
[USB]addr: 0x22, value: %x
", var);
+ //print("
[USB]addr: 0x22, value: %x
", var);
USBPHY_I2C_WRITE8(0x22, var & ~0x02);
USBPHY_I2C_READ8(0x22, &var);
- print("
[USB]addr: 0x22, value after: %x
", var);
+ //print("
[USB]addr: 0x22, value after: %x
", var);
#endif
var = READ_REG(UART1_BASE + 0xB0);
- print("
[USB]addr: 0x110020B0 (UART1), value: %x
", var);
+ //print("
[USB]addr: 0x110020B0 (UART1), value: %x
", var);
WRITE_REG(var & ~0x01, UART1_BASE + 0xB0);
- print("
[USB]addr: 0x110020B0 (UART1), value after: %x
", READ_REG(UART1_BASE + 0xB0));
+ //print("
[USB]addr: 0x110020B0 (UART1), value after: %x
", READ_REG(UART1_BASE + 0xB0));
}
void set_to_uart_mode(void)
@@ -297,74 +298,74 @@ void set_to_uart_mode(void)
#if !CFG_FPGA_PLATFORM
/* Turn on USB MCU Bus Clock */
var = READ_REG(PERI_GLOBALCON_PDN0_SET);
- print("
[USB]USB bus clock: 0x008, value: %x
", var);
+ //print("
[USB]USB bus clock: 0x008, value: %x
", var);
USB_CLR_BIT(USB0_PDN, PERI_GLOBALCON_PDN0_SET);
var = READ_REG(PERI_GLOBALCON_PDN0_SET);
- print("
[USB]USB bus clock: 0x008, value after: %x
", var);
+ //print("
[USB]USB bus clock: 0x008, value after: %x
", var);
/* Switch from BC1.1 mode to USB mode */
var = USBPHY_READ8(0x1A);
- print("
[USB]addr: 0x1A, value: %x
", var);
+ //print("
[USB]addr: 0x1A, value: %x
", var);
USBPHY_WRITE8(0x1A, var & 0x7f);
- print("
[USB]addr: 0x1A, value after: %x
", USBPHY_READ8(0x1A));
+ //print("
[USB]addr: 0x1A, value after: %x
", USBPHY_READ8(0x1A));
/* Set ru_uart_mode to 2'b01 */
var = USBPHY_READ8(0x6B);
- print("
[USB]addr: 0x6B, value: %x
", var);
+ //print("
[USB]addr: 0x6B, value: %x
", var);
USBPHY_WRITE8(0x6B, var | 0x5C);
- print("
[USB]addr: 0x6B, value after: %x
", USBPHY_READ8(0x6B));
+ //print("
[USB]addr: 0x6B, value after: %x
", USBPHY_READ8(0x6B));
/* Set RG_UART_EN to 1 */
var = USBPHY_READ8(0x6E);
- print("
[USB]addr: 0x6E, value: %x
", var);
+ //print("
[USB]addr: 0x6E, value: %x
", var);
USBPHY_WRITE8(0x6E, var | 0x07);
- print("
[USB]addr: 0x6E, value after: %x
", USBPHY_READ8(0x6E));
+ //print("
[USB]addr: 0x6E, value after: %x
", USBPHY_READ8(0x6E));
/* Set RG_USB20_DM_100K_EN to 1 */
var = USBPHY_READ8(0x22);
- print("
[USB]addr: 0x22, value: %x
", var);
+ //print("
[USB]addr: 0x22, value: %x
", var);
USBPHY_WRITE8(0x22, var | 0x02);
- print("
[USB]addr: 0x22, value after: %x
", USBPHY_READ8(0x22));
+ //print("
[USB]addr: 0x22, value after: %x
", USBPHY_READ8(0x22));
/* Set RG_SUSPENDM to 1 */
var = USBPHY_READ8(0x68);
- print("
[USB]addr: 0x68, value: %x
", var);
+ //print("
[USB]addr: 0x68, value: %x
", var);
USBPHY_WRITE8(0x68, var | 0x08);
- print("
[USB]addr: 0x68, value after: %x
", USBPHY_READ8(0x68));
+ //print("
[USB]addr: 0x68, value after: %x
", USBPHY_READ8(0x68));
/* force suspendm = 1 */
var = USBPHY_READ8(0x6A);
- print("
[USB]addr: 0x6A, value: %x
", var);
+ //print("
[USB]addr: 0x6A, value: %x
", var);
USBPHY_WRITE8(0x6A, var | 0x04);
- print("
[USB]addr: 0x6A, value after: %x
", USBPHY_READ8(0x6A));
+ //print("
[USB]addr: 0x6A, value after: %x
", USBPHY_READ8(0x6A));
#else
/* Set ru_uart_mode to 2'b01 */
USBPHY_I2C_READ8(0x6B, &var);
- print("
[USB]addr: 0x6B, value: %x
", var);
+ //print("
[USB]addr: 0x6B, value: %x
", var);
USBPHY_I2C_WRITE8(0x6B, var | 0x7C);
USBPHY_I2C_READ8(0x6B, &var);
- print("
[USB]addr: 0x6B, value after: %x
", var);
+ //print("
[USB]addr: 0x6B, value after: %x
", var);
/* Set RG_UART_EN to 1 */
USBPHY_I2C_READ8(0x6E, &var);
- print("
[USB]addr: 0x6E, value: %x
", var);
+ //print("
[USB]addr: 0x6E, value: %x
", var);
USBPHY_I2C_WRITE8(0x6E, var | 0x07);
USBPHY_I2C_READ8(0x6E, &var);
- print("
[USB]addr: 0x6E, value after: %x
", var);
+ //print("
[USB]addr: 0x6E, value after: %x
", var);
/* Set RG_USB20_DM_100K_EN to 1 */
USBPHY_I2C_READ8(0x22, &var);
- print("
[USB]addr: 0x22, value: %x
", var);
+ //print("
[USB]addr: 0x22, value: %x
", var);
USBPHY_I2C_WRITE8(0x22, var | 0x02);
USBPHY_I2C_READ8(0x22, &var);
- print("
[USB]addr: 0x22, value after: %x
", var);
+ //print("
[USB]addr: 0x22, value after: %x
", var);
#endif
mdelay(100);
var = DRV_Reg32(UART0_BASE+0xB0);
- print("
[USB]addr: 0x110020B0 (UART1), value: %x
", var);
+ //print("
[USB]addr: 0x110020B0 (UART1), value: %x
", var);
DRV_WriteReg32(UART0_BASE+0xB0, 0x0001);
- print("
[USB]addr: 0x110020B0 (UART1), value after: %x
", DRV_Reg32(UART0_BASE+0xB0));
+ //print("
[USB]addr: 0x110020B0 (UART1), value after: %x
", DRV_Reg32(UART0_BASE+0xB0));
}
extern U32 PMIC_VUSB_EN(void);
@@ -380,10 +381,10 @@ void platform_vusb_on(void)
(kal_uint32)(MT6331_PMIC_RG_VUSB10_EN_SHIFT)
);
if (ret==0){
- print("[platform_vusb_on] VUSB10 is on
");
+ //print("[platform_vusb_on] VUSB10 is on
");
}
else{
- print("[platform_vusb_on] Failed to turn on VUSB10!
");
+ //print("[platform_vusb_on] Failed to turn on VUSB10!
");
}*/
#if 0 //Disable temporarily to fix PMIC API missing build error.
ret = pmic_config_interface( (kal_uint32)(MT6325_LDO_CON9),
@@ -393,10 +394,10 @@ void platform_vusb_on(void)
);
if (ret==0){
- print("[platform_vusb_on] VUSB33 is on
");
+ //print("[platform_vusb_on] VUSB33 is on
");
}
else{
- print("[platform_vusb_on] Failed to turn on VUSB33!
");
+ //print("[platform_vusb_on] Failed to turn on VUSB33!
");
}
#else // Use New API instead, no need to change parameters if platform changed.
PMIC_VUSB_EN();
@@ -416,14 +417,14 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
tags->hdr.tag = BOOT_TAG_BOOT_REASON;
tags->u.boot_reason.boot_reason = g_boot_reason;
ptr += tags->hdr.size;
- print("boot reason: %d
", tags->u.boot_reason.boot_reason);
+ //print("boot reason: %d
", tags->u.boot_reason.boot_reason);
tags = ptr;
tags->hdr.size = boot_tag_size(boot_tag_boot_mode);
tags->hdr.tag = BOOT_TAG_BOOT_MODE;
tags->u.boot_mode.boot_mode = g_boot_mode;
ptr += tags->hdr.size;
- print("boot mode: %d
", tags->u.boot_mode.boot_mode);
+ //print("boot mode: %d
", tags->u.boot_mode.boot_mode);
tags = ptr;
tags->hdr.size = boot_tag_size(boot_tag_meta_com);
@@ -432,7 +433,7 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
tags->u.meta_com.meta_com_id = g_meta_com_id;
tags->u.meta_com.meta_uart_port = CFG_UART_META;
ptr += tags->hdr.size;
- print("META COM%d: %d
", tags->u.meta_com.meta_com_id, tags->u.meta_com.meta_com_type);
+ //print("META COM%d: %d
", tags->u.meta_com.meta_com_id, tags->u.meta_com.meta_com_type);
tags = ptr;
tags->hdr.size = boot_tag_size(boot_tag_log_com);
@@ -471,9 +472,9 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
tags->u.mem.tee_reserved_mem.size = bootarg.tee_reserved_mem.size;
ptr += tags->hdr.size;
for(i=0;i<tags->u.mem.mblock_info.mblock_num;i++) {
- print("rank[%d] size: 0x%x
", i, tags->u.mem.dram_rank_size[i]);
+ //print("rank[%d] size: 0x%x
", i, tags->u.mem.dram_rank_size[i]);
}
- print("tee reserved mem: 0x%llx, 0x%llx
", tags->u.mem.tee_reserved_mem.start, tags->u.mem.tee_reserved_mem.size);
+ //print("tee reserved mem: 0x%llx, 0x%llx
", tags->u.mem.tee_reserved_mem.start, tags->u.mem.tee_reserved_mem.size);
//----------------
tags = ptr;
@@ -484,7 +485,7 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
ptr += tags->hdr.size;
#if CFG_WORLD_PHONE_SUPPORT
for(i=0;i<2;i++)
- print("md_type[%d]: 0x%x
", i, tags->u.md_info.md_type[i]);
+ //print("md_type[%d]: 0x%x
", i, tags->u.md_info.md_type[i]);
#endif
tags = ptr;
@@ -492,7 +493,7 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
tags->hdr.tag = BOOT_TAG_BOOT_TIME;
tags->u.boot_time.boot_time = get_timer(g_boot_time);;
ptr += tags->hdr.size;
- print("boot time: %d
", tags->u.boot_time.boot_time);
+ //print("boot time: %d
", tags->u.boot_time.boot_time);
tags = ptr;
tags->hdr.size = boot_tag_size(boot_tag_da_info);
@@ -535,14 +536,14 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
tags->u.ddr_reserve.ddr_reserve_enable = g_ddr_reserve_enable;
tags->u.ddr_reserve.ddr_reserve_success = g_ddr_reserve_success;
ptr += tags->hdr.size;
- print("DDR reserve mode: enable = %d, success = %d
", tags->u.ddr_reserve.ddr_reserve_enable, tags->u.ddr_reserve.ddr_reserve_success);
+ //print("DDR reserve mode: enable = %d, success = %d
", tags->u.ddr_reserve.ddr_reserve_enable, tags->u.ddr_reserve.ddr_reserve_success);
tags = ptr;
tags->hdr.size = boot_tag_size(boot_tag_dram_buf);
tags->hdr.tag = BOOT_TAG_DRAM_BUF;
tags->u.dram_buf.dram_buf_size = sizeof(dram_buf_t);
ptr += tags->hdr.size;
- print("dram buffer size: %d
", tags->u.dram_buf.dram_buf_size);
+ //print("dram buffer size: %d
", tags->u.dram_buf.dram_buf_size);
tags = ptr;
tags->hdr.size = boot_tag_size(boot_tag_ptp);
@@ -561,9 +562,9 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
tags->u.boot_opt.lk_boot_opt= g_lk_boot_opt;
tags->u.boot_opt.kernel_boot_opt = g_kernel_boot_opt;
ptr += tags->hdr.size;
- print("SMC: 0x%x
", tags->u.boot_opt.smc_boot_opt);
- print("LK: 0x%x
", tags->u.boot_opt.lk_boot_opt);
- print("KERNEL: 0x%x
", tags->u.boot_opt.kernel_boot_opt);
+ //print("SMC: 0x%x
", tags->u.boot_opt.smc_boot_opt);
+ //print("LK: 0x%x
", tags->u.boot_opt.lk_boot_opt);
+ //print("KERNEL: 0x%x
", tags->u.boot_opt.kernel_boot_opt);
tags = ptr;
tags->hdr.size = boot_tag_size(boot_tag_sram_info);
@@ -571,8 +572,8 @@ void platform_set_boot_args_by_atag(unsigned *ptr)
tags->u.sram_info.non_secure_sram_addr= CFG_NON_SECURE_SRAM_ADDR;
tags->u.sram_info.non_secure_sram_size = CFG_NON_SECURE_SRAM_SIZE;
ptr += tags->hdr.size;
- print("NONSEC SRAM Addr: 0x%x
", tags->u.sram_info.non_secure_sram_addr);
- print("NONSEC SRAM Size: 0x%x
", tags->u.sram_info.non_secure_sram_size);
+ //print("NONSEC SRAM Addr: 0x%x
", tags->u.sram_info.non_secure_sram_addr);
+ //print("NONSEC SRAM Size: 0x%x
", tags->u.sram_info.non_secure_sram_size);
/* END */
*ptr++ = 0;
@@ -643,7 +644,7 @@ u32 g_kernel_boot_opt;
if ( 0 == strcmp(bootimg_opt_str_array[i], bootimg_opt_buf))
{
g_smc_boot_opt = i;
- print("%s,%s,boot_opt=0x%x
", MOD, bootimg_opt_str_array[g_smc_boot_opt], g_smc_boot_opt);
+ //print("%s,%s,boot_opt=0x%x
", MOD, bootimg_opt_str_array[g_smc_boot_opt], g_smc_boot_opt);
break;
}
}
@@ -657,7 +658,7 @@ u32 g_kernel_boot_opt;
if ( 0 == strcmp(bootimg_opt_str_array[i], bootimg_opt_buf))
{
g_lk_boot_opt = i;
- print("%s,%s,boot_opt=0x%x
", MOD, bootimg_opt_str_array[g_lk_boot_opt], g_lk_boot_opt);
+ //print("%s,%s,boot_opt=0x%x
", MOD, bootimg_opt_str_array[g_lk_boot_opt], g_lk_boot_opt);
break;
}
}
@@ -671,7 +672,7 @@ u32 g_kernel_boot_opt;
if ( 0 == strcmp(bootimg_opt_str_array[i], bootimg_opt_buf))
{
g_kernel_boot_opt = i;
- print("%s,%s,boot_opt=0x%x
", MOD, bootimg_opt_str_array[g_kernel_boot_opt], g_kernel_boot_opt);
+ //print("%s,%s,boot_opt=0x%x
", MOD, bootimg_opt_str_array[g_kernel_boot_opt], g_kernel_boot_opt);
break;
}
}
@@ -701,11 +702,11 @@ void platform_set_boot_args(void)
#endif
#if CFG_BOOT_ARGUMENT_BY_ATAG
- print("
%s boot to LK by ATAG.
", MOD, g_boot_reason);
+ //print("
%s boot to LK by ATAG.
", MOD, g_boot_reason);
platform_set_boot_args_by_atag(&(g_dram_buf->boottag)); // set jump addr
#elif CFG_BOOT_ARGUMENT && !CFG_BOOT_ARGUMENT_BY_ATAG
- print("
%s boot to LK.
", MOD, g_boot_reason);
+ //print("
%s boot to LK.
", MOD, g_boot_reason);
bootarg.magic = BOOT_ARGUMENT_MAGIC;
bootarg.mode = g_boot_mode;
bootarg.e_flag = sp_check_platform();
@@ -717,7 +718,7 @@ void platform_set_boot_args(void)
bootarg.dram_rank_num = bootarg.mblock_info.mblock_num;
for (i = 0; i < bootarg.mblock_info.mblock_num; i++) {
bootarg.dram_rank_size[i] = bootarg.mblock_info.mblock[i].size;
- print("%s, rank[%d].size = 0x%llx
", __func__, i,
+ //print("%s, rank[%d].size = 0x%llx
", __func__, i,
(unsigned long long) bootarg.dram_rank_size[i]);
}
#endif
@@ -743,25 +744,25 @@ void platform_set_boot_args(void)
bootarg.non_secure_sram_addr = CFG_NON_SECURE_SRAM_ADDR;
bootarg.non_secure_sram_size = CFG_NON_SECURE_SRAM_SIZE;
- print("%s NON SECURE SRAM ADDR: 0x%x
", MOD, bootarg.non_secure_sram_addr);
- print("%s NON SECURE SRAM SIZE: 0x%x
", MOD, bootarg.non_secure_sram_size);
+ //print("%s NON SECURE SRAM ADDR: 0x%x
", MOD, bootarg.non_secure_sram_addr);
+ //print("%s NON SECURE SRAM SIZE: 0x%x
", MOD, bootarg.non_secure_sram_size);
#if CFG_WORLD_PHONE_SUPPORT
- print("%s md_type[0] = %d
", MOD, bootarg.md_type[0]);
- print("%s md_type[1] = %d
", MOD, bootarg.md_type[1]);
+ //print("%s md_type[0] = %d
", MOD, bootarg.md_type[0]);
+ //print("%s md_type[1] = %d
", MOD, bootarg.md_type[1]);
#endif
- print("
%s boot reason: %d
", MOD, g_boot_reason);
- print("%s boot mode: %d
", MOD, g_boot_mode);
- print("%s META COM%d: %d
", MOD, bootarg.meta_com_id, bootarg.meta_com_type);
- print("%s <0x%x>: 0x%x
", MOD, &bootarg.e_flag, bootarg.e_flag);
- print("%s boot time: %dms
", MOD, bootarg.boot_time);
- print("%s DDR reserve mode: enable = %d, success = %d
", MOD, bootarg.ddr_reserve_enable, bootarg.ddr_reserve_success);
- print("%s dram_buf_size: 0x%x
", MOD, bootarg.dram_buf_size);
- print("%s smc_boot_opt: 0x%x
", MOD, bootarg.smc_boot_opt);
- print("%s lk_boot_opt: 0x%x
", MOD, bootarg.lk_boot_opt);
- print("%s kernel_boot_opt: 0x%x
", MOD, bootarg.kernel_boot_opt);
- print("%s tee_reserved_mem: 0x%llx, 0x%llx
", MOD, bootarg.tee_reserved_mem.start, bootarg.tee_reserved_mem.size);
+ //print("
%s boot reason: %d
", MOD, g_boot_reason);
+ //print("%s boot mode: %d
", MOD, g_boot_mode);
+ //print("%s META COM%d: %d
", MOD, bootarg.meta_com_id, bootarg.meta_com_type);
+ //print("%s <0x%x>: 0x%x
", MOD, &bootarg.e_flag, bootarg.e_flag);
+ //print("%s boot time: %dms
", MOD, bootarg.boot_time);
+ //print("%s DDR reserve mode: enable = %d, success = %d
", MOD, bootarg.ddr_reserve_enable, bootarg.ddr_reserve_success);
+ //print("%s dram_buf_size: 0x%x
", MOD, bootarg.dram_buf_size);
+ //print("%s smc_boot_opt: 0x%x
", MOD, bootarg.smc_boot_opt);
+ //print("%s lk_boot_opt: 0x%x
", MOD, bootarg.lk_boot_opt);
+ //print("%s kernel_boot_opt: 0x%x
", MOD, bootarg.kernel_boot_opt);
+ //print("%s tee_reserved_mem: 0x%llx, 0x%llx
", MOD, bootarg.tee_reserved_mem.start, bootarg.tee_reserved_mem.size);
#endif
#if CFG_ENABLE_GPIO_CHK_POINT_WITH_UART_META
@@ -772,7 +773,7 @@ void platform_set_boot_args(void)
{
mt_set_gpio_out(GPIO_CMDAT1, GPIO_OUT_ONE);
}
- print("Check META GPIO
");
+ //print("Check META GPIO
");
// while(1);
#endif
}
@@ -819,7 +820,7 @@ void platform_wdt_kick(void)
#if CFG_DT_MD_DOWNLOAD
void platform_modem_download(void)
{
- print("[%s] modem download...
", MOD);
+ //print("[%s] modem download...
", MOD);
/* Switch to MT6261 USB:
* GPIO_USB_SW1(USB_SW1)=1 //GPIO115, GPIO48
@@ -897,7 +898,7 @@ void platform_modem_download(void)
mt_set_gpio_dir(GPIO_EXT_MD_RST, GPIO_DIR_IN);
#endif
- print("[%s] AP modem download done
", MOD);
+ //print("[%s] AP modem download done
", MOD);
//keep kick WDT to avoid HW WDT reset
while (1) {
platform_wdt_all_kick();
@@ -921,13 +922,13 @@ void platform_usbdl_flag_check()
void platform_usb_auto_detect_flow()
{
- print("USB DL Flag is %d when enter preloader
",g_usbdl_flag);
+ //print("USB DL Flag is %d when enter preloader
",g_usbdl_flag);
/*usb download flag haven't set */
if(g_usbdl_flag == 0 && g_boot_reason != BR_RTC){
/*set up usbdl flag*/
platform_safe_mode(1,CFG_USB_AUTO_DETECT_TIMEOUT_MS);
- print("Preloader going reset and trigger BROM usb auto detectiton!!
");
+ //print("Preloader going reset and trigger BROM usb auto detectiton!!
");
/*WDT by pass powerkey reboot*/
//keep the previous status, pass it into reset function
@@ -977,7 +978,7 @@ void platform_safe_mode(int en, u32 timeout)
void platform_emergency_download(u32 timeout)
{
/* enter download mode */
- print("%s emergency download mode(timeout: %ds).
", MOD, timeout / 1000);
+ //print("%s emergency download mode(timeout: %ds).
", MOD, timeout / 1000);
platform_safe_mode(1, timeout);
#if !CFG_FPGA_PLATFORM
@@ -1018,7 +1019,7 @@ static boot_reason_t platform_boot_status(void)
ulong begin = get_timer(0);
do {
if (rtc_boot_check()) {
- print("%s RTC boot!
", MOD);
+ //print("%s RTC boot!
", MOD);
return BR_RTC;
}
if(!kpoc_flag)
@@ -1026,7 +1027,7 @@ static boot_reason_t platform_boot_status(void)
} while (get_timer(begin) < 1000 && kpoc_flag);
#else
if (rtc_boot_check()) {
- print("%s RTC boot!
", MOD);
+ //print("%s RTC boot!
", MOD);
return BR_RTC;
}
@@ -1036,10 +1037,10 @@ static boot_reason_t platform_boot_status(void)
if (mtk_wdt_boot_check() == WDT_NORMAL_REBOOT) {
- print("%s WDT normal boot!
", MOD);
+ //print("%s WDT normal boot!
", MOD);
return BR_WDT;
} else if (mtk_wdt_boot_check() == WDT_BY_PASS_PWK_REBOOT){
- print("%s WDT reboot bypass power key!
", MOD);
+ //print("%s WDT reboot bypass power key!
", MOD);
return BR_WDT_BY_PASS_PWK;
}
BOOTING_TIME_PROFILING_LOG("check Boot status-WDT");
@@ -1047,7 +1048,7 @@ static boot_reason_t platform_boot_status(void)
#if !CFG_FPGA_PLATFORM
/* check power key */
if (mtk_detect_key(PL_PMIC_PWR_KEY) && hw_check_battery()) {
- print("%s Power key boot!
", MOD);
+ //print("%s Power key boot!
", MOD);
rtc_mark_bypass_pwrkey();
return BR_POWER_KEY;
}
@@ -1056,23 +1057,23 @@ static boot_reason_t platform_boot_status(void)
#if !CFG_EVB_PLATFORM
if (usb_accessory_in()) {
- print("%s USB/charger boot!
", MOD);
+ //print("%s USB/charger boot!
", MOD);
BOOTING_TIME_PROFILING_LOG("check Boot status-usb_accessory_in");
return BR_USB;
} else {
if (rtc_2sec_reboot_check()) {
- print("%s 2sec reboot!
", MOD);
+ //print("%s 2sec reboot!
", MOD);
BOOTING_TIME_PROFILING_LOG("check Boot status-rtc_2sec_reboot_check");
return BR_2SEC_REBOOT;
}
}
- print("%s Unknown boot!
", MOD);
+ //print("%s Unknown boot!
", MOD);
pl_power_off();
/* should nerver be reached */
#endif
- print("%s Power key boot!
", MOD);
+ //print("%s Power key boot!
", MOD);
return BR_POWER_KEY;
}
@@ -1115,16 +1116,16 @@ bool platform_com_wait_forever_check(void)
#ifdef USBDL_DETECT_VIA_KEY
/* check download key */
if (TRUE == mtk_detect_key(COM_WAIT_KEY)) {
- print("%s COM handshake timeout force disable: Key
", MOD);
+ //print("%s COM handshake timeout force disable: Key
", MOD);
return TRUE;
}
#endif
#ifdef USBDL_DETECT_VIA_AT_COMMAND
- print("platform_com_wait_forever_check
");
+ //print("platform_com_wait_forever_check
");
/* check SRAMROM_USBDL_TO_DIS */
if (USBDL_TO_DIS == (INREG32(SRAMROM_USBDL_TO_DIS) & USBDL_TO_DIS)) {
- print("%s COM handshake timeout force disable: AT Cmd
", MOD);
+ //print("%s COM handshake timeout force disable: AT Cmd
", MOD);
CLRREG32(SRAMROM_USBDL_TO_DIS, USBDL_TO_DIS);
return TRUE;
}
@@ -1201,7 +1202,7 @@ kal_uint32 fan5405_write_byte(kal_uint8 addr, kal_uint8 value)
len = 2;
ret_code = i2c_write(&fan5405_i2c, write_data, len);
- //dprintf(INFO, "%s: i2c_write: ret_code: %d
", __func__, ret_code);
+ //d//printf(INFO, "%s: i2c_write: ret_code: %d
", __func__, ret_code);
return ret_code;
}
@@ -1220,7 +1221,7 @@ kal_uint32 fan5405_read_byte (kal_uint8 addr, kal_uint8 *dataBuffer)
len = 1;
ret_code = i2c_write_read(&fan5405_i2c, dataBuffer, len, len);
- //dprintf(INFO, "%s: i2c_read: ret_code: %d
", __func__, ret_code);
+ //d//printf(INFO, "%s: i2c_read: ret_code: %d
", __func__, ret_code);
return ret_code;
}
@@ -1233,7 +1234,7 @@ unsigned int fan5405_reg_config_interface (unsigned char RegNum, unsigned char v
ret = fan5405_write_byte(RegNum, val);
if(g_fan5405_log_en>1)
- printf("%d
", ret);
+ //printf("%d
", ret);
return ret;
}
@@ -1242,24 +1243,24 @@ unsigned int fan5405_reg_config_interface (unsigned char RegNum, unsigned char v
//
void fan5405_hw_init(void)
{
- printf("fan5405_hw_init in preloader......
");
+ //printf("fan5405_hw_init in preloader......
");
kal_uint8 fan5405_reg = 0;
int ret = 0;
ret = fan5405_read_byte(0x06, &fan5405_reg);
- printf("[fan5405_config_interface] Reg[0x06] = 0x%x
", fan5405_reg);
+ //printf("[fan5405_config_interface] Reg[0x06] = 0x%x
", fan5405_reg);
if(fan5405_reg == 0x57)
{
fan5405_reg_config_interface(0x01, 0xf8);
- printf("[fan5405_config_interface]fan5405_reg == 0x4b Reg[0x06]= 0x%x
", fan5405_reg);
+ //printf("[fan5405_config_interface]fan5405_reg == 0x4b Reg[0x06]= 0x%x
", fan5405_reg);
}
else
{
fan5405_reg_config_interface(0x06, 0x57);//4.34v
fan5405_reg_config_interface(0x01, 0xf8);
- printf("fan5405_reg start not 0x77
");
+ //printf("fan5405_reg start not 0x77
");
}
fan5405_reg_config_interface(0x02, 0xaa);//4.34v
@@ -1312,10 +1313,10 @@ void platform_pre_init(void)
#if (CFG_USB_UART_SWITCH)
if (is_uart_cable_inserted()) {
- print("
%s Switch to UART Mode
", MOD);
+ //print("
%s Switch to UART Mode
", MOD);
set_to_uart_mode();
} else {
- print("
%s Keep stay in USB Mode
", MOD);
+ //print("
%s Keep stay in USB Mode
", MOD);
}
BOOTING_TIME_PROFILING_LOG("USB SWITCH to UART");
#endif
@@ -1343,8 +1344,17 @@ void platform_pre_init(void)
//modify by gyg end
#endif
#if !CFG_FPGA_PLATFORM
+//print("zoukai say hello preloader!!!");
pmic_ret = pmic_init();
-
+/*add by zoukai for ETT test*/
+ pmic_force_PWM_Mode();
+ pmic_HQA_Voltage_adjust(4); //hv
+// pmic_HQA_Voltage_adjust(1);
+// pmic_HQA_Voltage_adjust(2);
+// pmic_HQA_Voltage_adjust(3); //lv
+// pmic_HQA_Voltage_adjust(4); //nv
+pmic_voltage_read(0);
+////////////////////////////////
mt_pll_post_init();
//mt_arm_pll_sel();
BOOTING_TIME_PROFILING_LOG("PMIC");
@@ -1354,14 +1364,14 @@ void platform_pre_init(void)
PMIC_enable_long_press_reboot();
BOOTING_TIME_PROFILING_LOG("Long Pressed Reboot");
- print("%s Init I2C: %s(%d)
", MOD, i2c_ret ? "FAIL" : "OK", i2c_ret);
- print("%s Init PWRAP: %s(%d)
", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret);
- print("%s Init PMIC: %s(%d)
", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret);
+ //print("%s Init I2C: %s(%d)
", MOD, i2c_ret ? "FAIL" : "OK", i2c_ret);
+ //print("%s Init PWRAP: %s(%d)
", MOD, pwrap_ret ? "FAIL" : "OK", pwrap_ret);
+ //print("%s Init PMIC: %s(%d)
", MOD, pmic_ret ? "FAIL" : "OK", pmic_ret);
platform_core_handler();
- print("%s chip_code[%x]
", MOD, mt_get_chip_hw_code());
- print("%s chip_ver[%x]
", MOD, mt_get_chip_sw_ver());
+ //print("%s chip_code[%x]
", MOD, mt_get_chip_hw_code());
+ //print("%s chip_ver[%x]
", MOD, mt_get_chip_sw_ver());
//if (0x321 == mt_get_chip_hw_code()) {
if (!pmic_ret) // XXX: && !i2c_ret && !pwrap_ret, not set
@@ -1445,7 +1455,7 @@ void platform_init(void)
/* init device storeage */
ret = boot_device_init();
BOOTING_TIME_PROFILING_LOG("Boot dev init");
- print("%s Init Boot Device: %s(%d)
", MOD, ret ? "FAIL" : "OK", ret);
+ //print("%s Init Boot Device: %s(%d)
", MOD, ret ? "FAIL" : "OK", ret);
#if ((CFG_EMERGENCY_DL_SUPPORT) && (!CFG_FPGA_PLATFORM))
/* check if to enter emergency download mode */
@@ -1539,7 +1549,7 @@ void platform_post_init(void)
#if CFG_BATTERY_DETECT
/* normal boot to check battery exists or not */
if (g_boot_mode == NORMAL_BOOT && !hw_check_battery() && usb_accessory_in()) {
- print("%s Wait for battery inserted...
", MOD);
+ //print("%s Wait for battery inserted...
", MOD);
/* disable pmic pre-charging led */
pl_close_pre_chr_led();
/* enable force charging mode */
@@ -1616,7 +1626,7 @@ void platform_error_handler(void)
mtk_uart_init(UART_SRC_CLK_FRQ, CFG_LOG_BAUDRATE);
log_ctrl(1);
}
- print("PL fatal error...
");
+ //print("PL fatal error...
");
#if !CFG_FPGA_PLATFORM
sec_util_brom_download_recovery_check();
@@ -1625,7 +1635,7 @@ void platform_error_handler(void)
#if defined(ONEKEY_REBOOT_NORMAL_MODE_PL) || defined(TWOKEY_REBOOT_NORMAL_MODE_PL)
/* add delay for Long Preessed Reboot count down
only pressed power key will have this delay */
- print("PL delay for Long Press Reboot
");
+ //print("PL delay for Long Press Reboot
");
for ( i=3; i > 0;i-- ) {
if (mtk_detect_key(PL_PMIC_PWR_KEY)) {
platform_wdt_kick();
@@ -1646,7 +1656,7 @@ void platform_error_handler(void)
void platform_assert(char *file, int line, char *expr)
{
- print("<ASSERT> %s:line %d %s
", file, line, expr);
+ //print("<ASSERT> %s:line %d %s
", file, line, expr);
platform_error_handler();
}
@@ -1663,23 +1673,23 @@ int aarch64_slt_done(void)
{
ret_val=pmic_read_interface(0x4020, &value_pmic_reg, 0xFFFF, 0x0);
if (ret_val)
- print("[PMIC] Fail to get 0x4020 value
");
+ //print("[PMIC] Fail to get 0x4020 value
");
else
- print("[PMIC] 0x4020 = 0x%X
", value_pmic_reg);
+ //print("[PMIC] 0x4020 = 0x%X
", value_pmic_reg);
ret_val=pmic_config_interface(0x4020, 0x0000, 0x8000, 0);
if (ret_val)
- print("[PMIC] Fail to set 0x4020 value
");
+ //print("[PMIC] Fail to set 0x4020 value
");
ret_val=pmic_config_interface(0x403C, 0x0001, 0x0001, 0);
if (ret_val)
- print("[PMIC] Fail to set 0x403C value
");
+ //print("[PMIC] Fail to set 0x403C value
");
else {
ret_val=pmic_read_interface(0x4020, &tmp_pmic_reg, 0xFFFF, 0x0);
if (ret_val)
- print("[PMIC] Fail to get 0x4020 value
");
+ //print("[PMIC] Fail to get 0x4020 value
");
else
- print("[PMIC] 0x4020 = 0x%X
", tmp_pmic_reg);
+ //print("[PMIC] 0x4020 = 0x%X
", tmp_pmic_reg);
}
if (0x8000 & value_pmic_reg)
@@ -1693,24 +1703,24 @@ int aarch64_slt_done(void)
ret_val=pmic_read_interface(0x4020, &tmp_pmic_reg, 0xFFFF, 0x0);
if (ret_val)
- print("[PMIC] Fail to get 0x4020 value
");
+ //print("[PMIC] Fail to get 0x4020 value
");
else
- print("[PMIC] 0x4020 = 0x%X
", tmp_pmic_reg);
+ //print("[PMIC] 0x4020 = 0x%X
", tmp_pmic_reg);
if (0x8000 & tmp_pmic_reg) {
ret_val=pmic_config_interface(0x4020, 0x0000, 0x8000, 0);
if (ret_val)
- print("[PMIC] Fail to set 0x4020 value
");
+ //print("[PMIC] Fail to set 0x4020 value
");
ret_val=pmic_config_interface(0x403C, 0x0001, 0x0001, 0);
if (ret_val)
- print("[PMIC] Fail to set 0x403C value
");
+ //print("[PMIC] Fail to set 0x403C value
");
else {
ret_val=pmic_read_interface(0x4020, &tmp_pmic_reg, 0xFFFF, 0x0);
if (ret_val)
- print("[PMIC] Fail to get 0x4020 value
");
+ //print("[PMIC] Fail to get 0x4020 value
");
else
- print("[PMIC] 0x4020 = 0x%X
", tmp_pmic_reg);
+ //////print("[PMIC] 0x4020 = 0x%X
", tmp_pmic_reg);
}
}
diff --git a/bootable/bootloader/preloader/platform/mt6735/src/drivers/pmic_wrap_init.c b/bootable/bootloader/preloader/platform/mt6735/src/drivers/pmic_wrap_init.c
index 957a54b..aa6ce02 100644
--- a/bootable/bootloader/preloader/platform/mt6735/src/drivers/pmic_wrap_init.c
+++ b/bootable/bootloader/preloader/platform/mt6735/src/drivers/pmic_wrap_init.c
@@ -101,7 +101,7 @@ S32 pwrap_init ( void )
S32 pwrap_init_preloader ( void )
{
u32 pwrap_ret=0,i=0;
- PWRAPFUC();
+ ////PWRAPFUC();
for(i=0;i<3;i++)
{
pwrap_ret = pwrap_init();
@@ -136,16 +136,16 @@ void pwrap_init_for_early_porting(void)
{
int ret = 0;
U32 res=0;
- PWRAPFUC();
+ ////PWRAPFUC();
ret=_pwrap_status_update_test_porting();
if(ret==0)
{
- PWRAPLOG("wrapper_StatusUpdateTest pass.
");
+ //PWRAPLOG("wrapper_StatusUpdateTest pass.
");
}
else
{
- PWRAPLOG("error:wrapper_StatusUpdateTest fail.
");
+ //PWRAPLOG("error:wrapper_StatusUpdateTest fail.
");
res+=1;
}
@@ -404,7 +404,7 @@ S32 pwrap_wacs2( U32 write, U32 adr, U32 wdata, U32 *rdata )
//struct pmic_wrap_obj *pwrap_obj = g_pmic_wrap_obj;
//if (!pwrap_obj)
// PWRAPERR("NULL pointer
");
- //PWRAPFUC();
+ //////PWRAPFUC();
//PWRAPLOG("wrapper access,write=%x,add=%x,wdata=%x,rdata=%x
",write,adr,wdata,rdata);
// Check argument validation
@@ -482,7 +482,7 @@ static S32 _pwrap_wacs2_nochk( U32 write, U32 adr, U32 wdata, U32 *rdata )
U32 wacs_adr=0x0;
U32 wacs_cmd=0x0;
U32 return_value=0x0;
- //PWRAPFUC();
+ ////PWRAPFUC();
// Check argument validation
if( (write & ~(0x1)) != 0) return E_PWR_INVALID_RW;
if( (adr & ~(0xffff)) != 0) return E_PWR_INVALID_ADDR;
@@ -532,7 +532,7 @@ static S32 _pwrap_init_dio( U32 dio_en )
U32 rdata=0x0;
U32 return_value=0;
- //PWRAPFUC();
+ ////PWRAPFUC();
arb_en_backup = WRAP_RD32(PMIC_WRAP_HIPRIO_ARB_EN);
WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN , WACS2); // only WACS2
#ifdef SLV_6328
@@ -584,7 +584,7 @@ static S32 _pwrap_init_cipher( void )
U32 rdata=0;
U32 return_value=0;
U32 start_time_ns=0, timeout_ns=0;
- //PWRAPFUC();
+ ////PWRAPFUC();
arb_en_backup = WRAP_RD32(PMIC_WRAP_HIPRIO_ARB_EN);
WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN ,WACS2); // only WACS0
@@ -729,10 +729,10 @@ static S32 _pwrap_init_sistrobe( void )
#ifdef SLV_6332
_pwrap_wacs2_nochk(0, MT6332_DEW_READ_TEST, 0, &rdata);
if( rdata == MT6332_DEFAULT_VALUE_READ_TEST ) {
- PWRAPLOG("_pwrap_init_sistrobe [Read Test of MT6332] pass,index=%d rdata=%x
", ind,rdata);
+ //PWRAPLOG("_pwrap_init_sistrobe [Read Test of MT6332] pass,index=%d rdata=%x
", ind,rdata);
result[1] |= (0x1 << ind);
}else {
- PWRAPLOG("_pwrap_init_sistrobe [Read Test of MT6332] tuning,index=%d rdata=%x
", ind,rdata);
+ //PWRAPLOG("_pwrap_init_sistrobe [Read Test of MT6332] tuning,index=%d rdata=%x
", ind,rdata);
}
#endif
}
@@ -824,7 +824,7 @@ static S32 _pwrap_reset_spislv( void )
{
U32 ret=0;
U32 return_value=0;
- //PWRAPFUC();
+ ////PWRAPFUC();
// This driver does not using _pwrap_switch_mux
// because the remaining requests are expected to fail anyway
@@ -861,12 +861,12 @@ timeout:
static void __pwrap_soft_reset(void)
{
- PWRAPLOG("start reset wrapper
");
+ //PWRAPLOG("start reset wrapper
");
//PWRAP_SOFT_RESET;
WRAP_WR32(INFRA_GLOBALCON_RST0,0x80);
- PWRAPLOG("the reset register =%x
",WRAP_RD32(INFRA_GLOBALCON_RST0));
- PWRAPLOG("PMIC_WRAP_STAUPD_GRPEN =0x%x,it should be equal to 0xc
",WRAP_RD32(PMIC_WRAP_STAUPD_GRPEN));
+ //PWRAPLOG("the reset register =%x
",WRAP_RD32(INFRA_GLOBALCON_RST0));
+ //PWRAPLOG("PMIC_WRAP_STAUPD_GRPEN =0x%x,it should be equal to 0xc
",WRAP_RD32(PMIC_WRAP_STAUPD_GRPEN));
//clear reset bit
//PWRAP_CLEAR_SOFT_RESET_BIT;
WRAP_WR32(INFRA_GLOBALCON_RST1,0x80);
@@ -877,7 +877,7 @@ static S32 _pwrap_init_signature( U8 path )
{
int ret=0;
U32 rdata=0x0;
- PWRAPFUC();
+ ////PWRAPFUC();
if(path == 1){
//###############################
@@ -924,7 +924,7 @@ static S32 _pwrap_init_reg_clock( U32 regck_sel )
{
//U32 wdata=0;
//U32 rdata=0;
- PWRAPFUC();
+ ////PWRAPFUC();
// Set Dummy cycle 6328 and 6332 (assume 12MHz)
#ifdef SLV_6328
@@ -1056,7 +1056,7 @@ S32 pwrap_init ( void )
U32 rdata=0x0;
volatile U32 delay=1000*1000*1;
//U32 timeout=0;
- PWRAPFUC();
+ ////PWRAPFUC();
//###############################
//toggle PMIC_WRAP and pwrap_spictl reset
//###############################
@@ -1136,7 +1136,7 @@ S32 pwrap_init ( void )
// Enable Encryption
//###############################
- PWRAPLOG("have cipher
");
+ //PWRAPLOG("have cipher
");
sub_return = _pwrap_init_cipher();
if( sub_return != 0 )
{
@@ -1180,7 +1180,7 @@ S32 pwrap_init ( void )
PWRAPERR("Enable CRC fail, return=%x
", sub_return);
return E_PWR_INIT_ENABLE_CRC;
}
- PWRAPLOG("mt_pwrap_init PMIC_WRAP_STAUPD_GRPEN(%x)
",WRAP_RD32(PMIC_WRAP_STAUPD_GRPEN));
+ //PWRAPLOG("mt_pwrap_init PMIC_WRAP_STAUPD_GRPEN(%x)
",WRAP_RD32(PMIC_WRAP_STAUPD_GRPEN));
#endif
#if 1
@@ -1240,10 +1240,10 @@ S32 pwrap_init ( void )
//###############################
#if defined(MACH_TYPE_MT6735M)
WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN,0xff); //D2 change
- PWRAPLOG("mt_pwrap_init-- use D2
");
+ //PWRAPLOG("mt_pwrap_init-- use D2
");
#else
WRAP_WR32(PMIC_WRAP_HIPRIO_ARB_EN,0x3ff);
- PWRAPLOG("mt_pwrap_init-- use D1 or D3
");
+ //PWRAPLOG("mt_pwrap_init-- use D1 or D3
");
#endif
WRAP_WR32(PMIC_WRAP_WACS0_EN,ENABLE);
WRAP_WR32(PMIC_WRAP_WACS1_EN,ENABLE);
@@ -1280,7 +1280,7 @@ S32 pwrap_init ( void )
//PWRAPLOG("mt_pwrap_init---- debug14
");
WRAP_WR32(PMIC_WRAP_EINT_STA0_ADR,MT6328_INT_STA);
- PWRAPLOG("mt_pwrap_init---- debug15,%x
",WRAP_RD32(PMIC_WRAP_INT_EN));
+ //PWRAPLOG("mt_pwrap_init---- debug15,%x
",WRAP_RD32(PMIC_WRAP_INT_EN));
pwrap_ut(1);
pwrap_ut(2);
return 0;
@@ -1318,7 +1318,7 @@ void pwrap_dump_ap_register(void)
S32 pwrap_init_preloader ( void )
{
u32 pwrap_ret=0,i=0;
- PWRAPFUC();
+ ////PWRAPFUC();
for(i=0;i<3;i++)
{
pwrap_ret = pwrap_init();
@@ -1350,7 +1350,7 @@ static S32 _pwrap_status_update_test_porting( void )
U32 i, j;
U32 rdata;
volatile U32 delay=1000*1000*1;
- PWRAPFUC();
+ ////PWRAPFUC();
//disable signature interrupt
WRAP_WR32(PMIC_WRAP_INT_EN,0x0);
#ifdef SLV_6325
@@ -1410,16 +1410,16 @@ void pwrap_init_for_early_porting(void)
{
int ret = 0;
U32 res=0;
- PWRAPFUC();
+ ////PWRAPFUC();
ret=_pwrap_status_update_test_porting();
if(ret==0)
{
- PWRAPLOG("wrapper_StatusUpdateTest pass.
");
+ //PWRAPLOG("wrapper_StatusUpdateTest pass.
");
}
else
{
- PWRAPLOG("error:wrapper_StatusUpdateTest fail.
");
+ //PWRAPLOG("error:wrapper_StatusUpdateTest fail.
");
res+=1;
}
diff --git a/kernel-3.10/drivers/misc/mediatek/dramc/mt6735/mt_dramc.c b/kernel-3.10/drivers/misc/mediatek/dramc/mt6735/mt_dramc.c
index 66f7cb1..839e7f6 100644
--- a/kernel-3.10/drivers/misc/mediatek/dramc/mt6735/mt_dramc.c
+++ b/kernel-3.10/drivers/misc/mediatek/dramc/mt6735/mt_dramc.c
@@ -26,6 +26,8 @@
#include <linux/of.h>
#include <linux/of_address.h>
+#include <mach/mt_dramc.h>
+
#ifdef FREQ_HOPPING_TEST
#include <mach/mt_freqhopping.h>
#endif
@@ -76,13 +78,13 @@ void pmic_voltage_read(unsigned int nAdjust)
unsigned int OldVcore1 = 0;
unsigned int OldVmem = 0, OldVmem1 = 0;
- pr_info("[PMIC]pmic_voltage_read : \r
");
+ printk("[PMIC]pmic_voltage_read : \r
");
ret_val = pmic_read_interface(MT6328_VCORE1_CON11, &OldVcore1, 0x7F, 0);
ret_val = pmic_read_interface(MT6328_SLDO_ANA_CON0, &OldVmem, 0x7F, 0);
ret_val = pmic_read_interface(MT6328_SLDO_ANA_CON1, &OldVmem1, 0x0F, 8);
- pr_info("[Vcore] MT6328_VCORE1_CON11=0x%x,\r
[Vmem] MT6328_SLDO_ANA_CON0/1=0x%x 0x%x\r
",
+ printk("[Vcore] MT6328_VCORE1_CON11=0x%x,\r
[Vmem] MT6328_SLDO_ANA_CON0/1=0x%x 0x%x\r
",
OldVcore1, OldVmem, OldVmem1);
}
diff --git a/kernel-3.10/drivers/misc/mediatek/power/mt6735/pmic.c b/kernel-3.10/drivers/misc/mediatek/power/mt6735/pmic.c
index ef539b5..1749304 100644
--- a/kernel-3.10/drivers/misc/mediatek/power/mt6735/pmic.c
+++ b/kernel-3.10/drivers/misc/mediatek/power/mt6735/pmic.c
@@ -80,6 +80,7 @@
#include <cust_pmic.h>
#include <cust_eint.h>
#include <cust_battery_meter.h>
+#include <mach/mt_dramc.h>
//==============================================================================
@@ -4221,7 +4222,12 @@ static int pmic_mt_probe(struct platform_device *dev)
PMIC_CUSTOM_SETTING_V1();
PMICLOG("[PMIC_CUSTOM_SETTING_V1] Done
");
-
+ pmic_HQA_Voltage_adjust(4); //hv
+// pmic_HQA_Voltage_adjust(1);
+// pmic_HQA_Voltage_adjust(2);
+ // pmic_HQA_Voltage_adjust(3); //lv
+// pmic_HQA_Voltage_adjust(4); //nv
+ pmic_voltage_read(0);
//#if defined(CONFIG_MTK_FPGA)
#if 0
PMICLOG("[PMIC_EINT_SETTING] disable when CONFIG_MTK_FPGA
");