トリプルステートキャッシュTri-state buffer

1. Tri-state buffer logic function

Tri-state buffer acts as a switch in digital circuit by isolating a signal path in a circuit. This switch can attain three logical states. The three states are 0, 1 and ‘Z’. The logical state 0 and 1 are possible when the switch is CLOSE(スイッチオフ).The logical value‘Z’or high impedance is attained when switch is OPEN(スイッチオフ).So when switch is open the input to tristate buffer is isolated from the circuit and output can be driven by some other logical path on a shared connection/bus. 
Depending on the active level of ENA, there are two kind of tri-state buffer: tri-state buffer with high-active ENA, inverting tri-state buffer with low-active ENA. Their truth-tables are shown as below:
 
Truth table for tri-state buffer
ENA
In
Out
0
0
Z
0
1
Z
1
0
0
1
1
1
Truth-table for inverting tri-state buffer
ENA
In
Out
0
0
0
0
1
1
1
0
Z
1
1
Z
 

2. Verilog example

// Tristate Buffer
module tristate_buffer(input_x, enable, output_x);
    input input_x;
    input enable;
    output output_x;

    assign output_x = enable? input_x : 'bz;

endmodule

 

3. tri-state usage

Tristate buffers can be used for shared bus interfaces, bidirectional IOs and shared memory interfaces. These onchip implementations allows bi-directional IO’s to switch polarities from input to output. Also when used on external chip-memory interface, these can switch to floating or high Z outputs to allow other devices on the same shared bus to access same memory.
最も基本的な応用例は、I 2 CバスのSDA信号線である.SDAは双方向信号線であり、I 2 CマスターとI 2 C slaveの間のデータ信号はSDAを介して伝送され、masterがslaveにデータを送信したり、masterがslaveからデータを受信したりする.双方向三状態IOポートをシミュレートするためのverilogモデルを以下に示す.

// Bi-Directional Tristate Buffer to modelling bi-directional IO.
module BIDIR_TRISTATE_BUF
#(
    parameter    P_WIDTH   = 8'd1       //  
)
(
    input               tx_enable, 

    input [P_WIDTH-1:0] tx_data  , 
    output[P_WIDTH-1:0] rx_data  , 

    inout [P_WIDTH-1:0] bidir_x);    
     
    assign bidir_x = tx_enable? tx_data : {P_WIDTH{'bz}};
    
    assign rx_data = {P_WIDTH{~tx_enable}}&bidir_x;
    
endmodule

I 2 Cバスモデリングでは、Master端子とSlave端子がそれぞれ1つのBIDIR_をインスタンス化するTRISTATE_BUF、SDAをbidir_に接続x端子は、そのまま接続することで双方向(半二重通信)を実現します.