チーム内部研修-PCIe P 2 P伝送ソフトウェア設計について

トレーニングプロセスの記録

|   DDR(eg. 2GB)   |      |     DDR(eg. 8GB) |
        |                           |
||||||||||||||||||||      ||||||||||||||||||||
|       Z7         |      |         V7       |
|       CPU        | PCIe |        DMA       |-|SATA Disk|
|       DMA        |      |                  | 
||||||||||||||||||||      ||||||||||||||||||||

DMA：Direct Memory Access
non OS:
unsigned int *buf = (unsigned int *)0x50000000 //phy
*buf -> ldr      

OS:
unsigned int *buf = malloc(64); //virt

V7  PCIe Z7   64MB    

CPU  OS              ，             Cache
CPU -> Cache -> Memory(DDR/PCIe)
CPU -> Memory(DDR/PCIe)

       Cache   ，  Cache   
eg.   /IP        Cache

     CPU  DMA           
Direct:       
Source -> Destination

SG:                   
| Descriptor0 | Descriptor1 | Descriptor2 | ... | DescriptorN |  
  Src -> Dst    Src -> Dst    Src -> Dst          Src -> Dst   

           1MB，SG Direct    ？
Direct    1MB  ，SG 1MB      5  ，5*64B，   1MB，5*64B/1MB~0%

                 8GB DDR
                  V7_1
                   |
 Z7(host)  --  PCIe Switch   --  V7_2 8GB DDR
             /      |     \  
           NVMe_1 NVMe_2 NVMe_3
           
CPU    （    ）
0
         DDR
2GB           
         PCIe   0~64MB(BAR0，    ) 64~65(BAR1，     ) V7_1            64~128 V7_2 128~129 NVMe_1 129~130 NVMe_2...    
                0x6c000000~0x6d000000      
2GB+1GB

   64MB      V7   8GB    ，    FPGA        ，  64MB      8GB       
FPGA            base

|64MB|
   |
    -----------
         base+ |    
|   |   |    |64MB|           8GB                |

                       0x6c000000~0x6d000000 0~64MB
CPU   addr0(    ) -> addr1(    ) -> addr2(8GB     )
                                          |
                                         base

P2P:
NVMe_1(    DMA) -> addr1 -> addr2(8GB     )
                     |
                    base
CRP PCIMEM    base
V7_1                    
PLCIRCBUF0 = {   0GB, 1GB  , add &PCIMEM0}
PLCIRCBUF1 = {   1GB, 1GB  , add &PCIMEM0}
PLCIRCBUF2 = {   2GB, 1GB  , add &PCIMEM0}

jsfsWrite(buf, len) buf > 64MB    ，    buf        ，          ， 0~8GB      0x6c000000~0x6d000000   
V7_2                    
PLCIRCBUF3 = {   0GB, 1GB  , add &PCIMEM1}
PLCIRCBUF4 = {   1GB, 1GB  , add &PCIMEM1}
PLCIRCBUF5 = {   2GB, 1GB  , add &PCIMEM1}

       1GB+1MB    0x40100000，        ：
offset = 0x40100000 & 64MB = 0x100000 1MB
base = 0x40100000 - offset = 0x40000000
jsfsWrite(0x6c000000 + offset, len)
or
base = 0x40100000
jsfsWrite(0x6c000000, len)

 ft2000/4 ，jsfsWrite     buf       ，64MB    ，
ipraid_write()/nvme_write()   CPU DDR           ，   FPGA DDR          
                 CPU DDR  FPGA DDR，  FPGA DDR，              ，   ipraid_write()/nvme_write()