コンピュータの構成の原理の実験の1 VHDL BCDコード

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bcd is

	port 
	(
		a,b		: in std_logic_vector(7 downto 0);
		s		: in std_logic_vector(7 downto 0);
		co		: out std_logic
	);

end entity;

architecture rtl of bcd is

	signal al,bl,sl,ah,bh,sh: std_logic_vector(4 downto 0);

begin

	process (a,b)
	begin
		al <= '0' & a(3 downto 0);
		bl <= '0' & b(3 downto 0);
		sl <= al + bl;
		
		if sl > "01001" then
			sl <= al + bl + "0110";
		end if;
	end process;

	process (a,b)
	begin
		ah <= '0' & a(7 downto 4);
		bh <= '0' & b(7 downto 4);
		sh <= ah + bh + sl(4);
		
		if sh > "01001" then
			sh <= ah + bh + sl(4) + "0110";
		end if;
	end process;
	
	s <= sh(3 downto 0) & sl(3 downto 0);
	co <= sh(4);
	
end rtl;